Description
I am curious on your thoughts in allowing pyVHDLModel to be used in analyzing partial (missing files) or mixed language projects. Currently, the Analyze function in __init__.py
will raise an exception if a package, library, or entity is missing and full analysis cannot be performed. As a local test, I removed raising some of the exceptions, and instead just printed them to know what is missing. I am using these changes with success in my use case.
Is this something which you would be open to being added to pyVHDLModel? I would need to think on a better long term way to allow for disabling the hard checks in analysis. I see value in doing so, especially in mixed language projects, or projects which use vendor provided libraries or entities which may not have plaintext source, or source that is only in Verilog.