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Missing syntactical elements for VHDL 2008 #225

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@Schottkyc137

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@Schottkyc137

The following is a list of elements that are currently not syntactically analyzed. Mostly this is because these elements are rarely used. However, for full compliance with the standard, these should be analyzed eventually.
Some of these can also be a starting point for new developers as these features (e.g., groups) are usually small and self-contained.
Below are also minimal reproducible examples that do not parse as of today.

This is also a good place to request prioritization on a feature if this feature is needed in a codebase.

  • Package declaration inside a declarative part
    entity ent is
    end entity;
    
    architecture arch of ent is
      package my_pkg is
          -- ...
       end package;
    begin
    end arch;
  • Package body inside a declarative part
    entity ent is
    end entity;
    
    architecture arch of ent is
      package my_pkg is
          -- ...
       end my_pkg;
      package body my_pkg is
          -- ...
       end package body;
    begin
    end arch;
  • Disconnect Specification
    disconnect sig after 100 ns;
  • Missing keywords and context where they are used
    • Sequence
    • Property
  • Group declaration
    group my_group : template_name ( A, B ) ;
  • Group template declaration
    group template_name is ( sequence, function ) ;
  • Concurrent select guarded and force assignment
    with a select b <= force c when d, e when f;
    with a select b <= guarded c when d, e when f;
  • Question mark after select
    with a select? b <= c when d, e when f;
  • Release assignment
    a <= release out;

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