Set up write back stage

src/interfaces/mem_to_wb_if.svh

@@ -0,0 +1,24 @@
+`ifndef MEM_TO_WB_IF__HG
+`define MEM_TO_WB_IF__HG
+
+interface mem_to_wb_if;
+
+  data_t read_data;
+  data_t alu_result;
+  logic [4:0] rd;
+
+  modport from_memory
+    ( input read_data
+    , input alu_result
+    , input rd
+    );
+
+  modport to_write_back
+    ( output read_data
+    , output alu_result
+    , output rd
+    );
+
+endinterface
+
+`endif MEM_TO_WB_IF__HG

src/stages/write_back.sv

@@ -0,0 +1,23 @@
+`default_nettype none
+
+module write_back
+  ( input var logic clk
+  , input var logic reset
+
+  , mem_to_wb_if.from_memory memory
+
+  , output var data_t      result
+  , output var logic [4:0] rd
+  );
+
+  assign rd = memory.rd;
+
+  // TODO: `REULST_SRC__ALU_OUT` is no longer covered, revisit during integration
+  always_comb
+    case (cfsm__result_src)
+      RESULT_SRC__DATA:       result = data;
+      RESULT_SRC__ALU_RESULT: result = alu_result;
+      default:                result = 32'hxxxxxxxx;
+    endcase
+
+endmodule