Improve rom verilog output

[vegaluisjose]

This improves rom verilog output by emitting the "always block" if and only if there are writes. For example, the following:

// Memory mem_0: tmp4
always @(posedge clk)
begin
end
assign tmp29 = mem_0[tmp28];
assign tmp30 = mem_0[tmp27];

is now emitted as:

// Memory mem_0: tmp4
assign tmp29 = mem_0[tmp28];
assign tmp30 = mem_0[tmp27];

[codecov-commenter]

Codecov Report

Merging #399 (e3cbf0c) into development (0e6fdae) will increase coverage by 0.00%.
The diff coverage is 100.00%.

@@             Coverage Diff              @@
##           development     #399   +/-   ##
============================================
  Coverage        90.71%   90.71%           
============================================
  Files               24       24           
  Lines             5988     5990    +2     
============================================
+ Hits              5432     5434    +2     
  Misses             556      556           

Impacted Files	Coverage Δ
pyrtl/importexport.py	85.67% <100.00%> (+0.04%)	⬆️

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[mdko]

Looks good, thank you!

[mdko]

FYI I merged your PR, and also just noticed a few more improvements that could be made (and merged them in #400). Thanks again!