A highly clock-accurate FPGA clone of the NES/Famicom 2A03(7) APU (pAPU), created on the basis of reverse engineering. All information about the internal structure can be found here: https://github.com/emu-russia/breaks/tree/master/BreakingNESWiki/APU
This core is multi-regional, switching between NTSC and PAL regions is available, with changes in the corresponding operating timings. All PLAs are packaged in m4k (m9k) blocks with mif initialization files.
Logisim circuit
Quartus circuit
Schematic diagram of the APU substitute for the FPGA.
photo of the prototype
Video on YouTube https://www.youtube.com/watch?v=RvPh_PWV7ng