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Remove gf12 wrappers #2638

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443e1a3
init
osamahammad21 Nov 7, 2024
43231fe
update OR
osamahammad21 Nov 11, 2024
2525100
Merge remote-tracking branch 'origin/master' into secure-remove-wrappers
osamahammad21 Nov 11, 2024
5140461
Merge remote-tracking branch 'origin/master' into secure-remove-wrappers
osamahammad21 Nov 18, 2024
9e84a29
support WidthTableOrth
osamahammad21 Nov 18, 2024
15d433c
update OR
osamahammad21 Nov 18, 2024
9a725d9
update OR
osamahammad21 Dec 1, 2024
2d8abce
move macro lefs and libs to additionals
osamahammad21 Dec 1, 2024
073e7c7
update OR
osamahammad21 Dec 16, 2024
431d710
Merge remote-tracking branch 'origin/master' into secure-remove-wrappers
osamahammad21 Dec 16, 2024
8295144
update OR
osamahammad21 Dec 17, 2024
afc93db
Merge remote-tracking branch 'origin/master' into secure-remove-wrappers
osamahammad21 Dec 17, 2024
94bb402
fix ca53 config and update swerv_wrapper limits
osamahammad21 Dec 17, 2024
651b316
move ca53 gds
osamahammad21 Dec 23, 2024
4df707f
Merge remote-tracking branch 'origin/master' into secure-remove-wrappers
osamahammad21 Jan 12, 2025
4292ee9
update OR
osamahammad21 Jan 21, 2025
6e8557d
Merge remote-tracking branch 'origin/master' into secure-remove-wrappers
osamahammad21 Jan 21, 2025
7e9996d
Merge remote-tracking branch 'origin/master' into secure-remove-wrappers
osamahammad21 Mar 27, 2025
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5 changes: 2 additions & 3 deletions flow/designs/gf12/ariane/config.mk
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Expand Up @@ -11,9 +11,9 @@ export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/ariane.sv2v.v \
#export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint_hier.sdc

export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12lp_1rf_lg8_w64_byte.lef
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/gf12lp_1rf_lg8_w64_byte.lef

export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12lp_1rf_lg8_w64_byte_sspg_sigcmax_0p72v_0p72v_125c.lib
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/gf12lp_1rf_lg8_w64_byte_sspg_sigcmax_0p72v_0p72v_125c.lib

export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12lp_1rf_lg8_w64_byte.gds2

Expand All @@ -28,7 +28,6 @@ export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl
export GPL_KEEP_OVERFLOW = 0

export MACRO_PLACE_HALO = 7 7
export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl

ifeq ($(USE_FILL),1)
export DESIGN_TYPE = CELL
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4 changes: 2 additions & 2 deletions flow/designs/gf12/ariane133/config.mk
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Expand Up @@ -9,8 +9,8 @@ export VERILOG_FILES = $(PLATFORM_DIR)/ariane133/ariane.v

export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/ariane133/ariane.sdc

export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rw_256x16.lef
export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rw_256x16_ffpg_sigcmin_0p88v_0p88v_m40c.lib
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/gf12_1rw_256x16.lef
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/gf12_1rw_256x16_ffpg_sigcmin_0p88v_0p88v_m40c.lib

export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12lp_1rf_lg8_w64_byte.gds2 \
$(PLATFORM_DIR)/gds/gf12_1rw_256x16.gds2
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13 changes: 5 additions & 8 deletions flow/designs/gf12/bp_dual/config.mk
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Expand Up @@ -21,25 +21,23 @@ export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/bsg_c

export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/bsg_chip.elab.v.sdc

export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \
$(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef \
$(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d128_w116_m2_bit.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d256_w48_m2.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d512_w64_m2_byte.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w124_m2_bit.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w62_m2_bit.lef

export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \
$(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef

export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib \
$(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d128_w116_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d256_w48_m2_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d512_w64_m2_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w124_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w62_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib

export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib

export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \
$(PLATFORM_DIR)/gds/gf12_1rw_d128_w116_m2_bit.gds2 \
$(PLATFORM_DIR)/gds/gf12_1rw_d256_w48_m2.gds2 \
Expand All @@ -61,7 +59,6 @@ export ABC_CLOCK_PERIOD_IN_PS = 1250
export TNS_END_PERCENT = 0
export PLACE_DENSITY = 0.50

export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl

export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl

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32 changes: 15 additions & 17 deletions flow/designs/gf12/bp_quad/config.mk
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Expand Up @@ -23,22 +23,21 @@ export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0

export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bsg_chip.elab.v.sdc

export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d128_w116_m2_bit.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d256_w48_m2.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d512_w64_m2_byte.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w124_m2_bit.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w62_m2_bit.lef

export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \
$(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef

export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d128_w116_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d256_w48_m2_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d512_w64_m2_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w124_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w62_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d128_w116_m2_bit.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d256_w48_m2.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d512_w64_m2_byte.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w124_m2_bit.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w62_m2_bit.lef \
$(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \
$(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef

export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d128_w116_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d256_w48_m2_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d512_w64_m2_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w124_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w62_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib

export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib

Expand All @@ -63,7 +62,6 @@ export ABC_CLOCK_PERIOD_IN_PS = 1250
export TNS_END_PERCENT = 0
export PLACE_DENSITY = 0.40

export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl

export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl

Expand Down
12 changes: 5 additions & 7 deletions flow/designs/gf12/bp_single/config.mk
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Expand Up @@ -11,24 +11,23 @@ export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_single_core_v0/yo

export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_single_core_v0/bsg_chip.elab.v.sdc

export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \
$(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef \
$(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d128_w116_m2_bit.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d256_w48_m2.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d512_w64_m2_byte.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w124_m2_bit.lef \
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w62_m2_bit.lef

export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \
$(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef

export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib \
$(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d128_w116_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d256_w48_m2_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d512_w64_m2_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w124_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w62_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib

export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib

export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \
$(PLATFORM_DIR)/gds/gf12_1rw_d128_w116_m2_bit.gds2 \
Expand All @@ -50,7 +49,6 @@ export ABC_CLOCK_PERIOD_IN_PS = 1250

export PLACE_DENSITY = 0.80

export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl
export RTLMP_FENCE_LX = 606.44
export RTLMP_FENCE_LY = 896.44
export RTLMP_FENCE_UX = 2449.96
Expand Down
52 changes: 24 additions & 28 deletions flow/designs/gf12/ca53/config.mk
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Expand Up @@ -7,32 +7,30 @@ export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v

export SDC_FILE = $(PLATFORM_DIR)/$(DESIGN_NAME)/sdc/ca53_cpu.sdc


export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sc9mcpp84_12lp_base_lvt_c14.lef
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sc9mcpp84_12lp_base_lvt_c14_tt_nominal_max_0p80v_25c.lib
export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sc9mcpp84_12lp_base_lvt_c14.gds2

export WRAP_LEFS = $(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1.lef

export WRAP_LIBS = $(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1_tt_nominal_0p80v_0p80v_25c.lib



export ADDITIONAL_GDS += $(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1.gds2 \
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sc9mcpp84_12lp_base_lvt_c14.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1.lef \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1.lef

export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sc9mcpp84_12lp_base_lvt_c14_tt_nominal_max_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1_tt_nominal_0p80v_0p80v_25c.lib



export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sc9mcpp84_12lp_base_lvt_c14.gds2 \
$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1.gds2 \
$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1.gds2 \
$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1.gds2 \
$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1.gds2 \
Expand All @@ -52,8 +50,6 @@ export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/ca53/io.tcl

export MACRO_PLACE_HALO = 7 7

export MACRO_WRAPPERS = $(dir $(DESIGN_CONFIG))/wrappers.tcl

#export MAX_ROUTING_LAYER = H2
export FASTROUTE_TCL = $(dir $(DESIGN_CONFIG))/fastroute.tcl
#
Expand Down
18 changes: 8 additions & 10 deletions flow/designs/gf12/coyote/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -8,15 +8,15 @@ export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/coyote.sv2v.v \
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export ABC_AREA = 1

export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w80_bit.lef \
$(PLATFORM_DIR)/lef/gf12_1rf_lg8_w128_all.lef \
$(PLATFORM_DIR)/lef/gf12_2rf_lg6_w44_bit.lef \
$(PLATFORM_DIR)/lef/gf12_2rf_lg8_w64_bit.lef
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w80_bit.lef \
$(PLATFORM_DIR)/lef/gf12_1rf_lg8_w128_all.lef \
$(PLATFORM_DIR)/lef/gf12_2rf_lg6_w44_bit.lef \
$(PLATFORM_DIR)/lef/gf12_2rf_lg8_w64_bit.lef

export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rf_lg6_w80_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rf_lg8_w128_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_2rf_lg6_w44_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_2rf_lg8_w64_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/gf12_1rf_lg6_w80_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rf_lg8_w128_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_2rf_lg6_w44_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_2rf_lg8_w64_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib

export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1rf_lg6_w80_bit.gds2 \
$(PLATFORM_DIR)/gds/gf12_1rf_lg8_w128_all.gds2 \
Expand All @@ -25,8 +25,6 @@ export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1rf_lg6_w80_bit.gds2 \

export PLACE_DENSITY = 0.35

export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl

export DIE_AREA = 0 0 752 752
export CORE_AREA = 2 2 750 750
export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl
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13 changes: 6 additions & 7 deletions flow/designs/gf12/swerv_wrapper/config.mk
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14,13 +14,13 @@ export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc

export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rf_lg11_w40_all.lef \
$(PLATFORM_DIR)/lef/gf12_1rf_lg6_w22_all.lef \
$(PLATFORM_DIR)/lef/gf12_1rf_lg8_w34_all.lef
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/gf12_1rf_lg11_w40_all.lef \
$(PLATFORM_DIR)/lef/gf12_1rf_lg6_w22_all.lef \
$(PLATFORM_DIR)/lef/gf12_1rf_lg8_w34_all.lef

export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rf_lg11_w40_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rf_lg6_w22_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rf_lg8_w34_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/gf12_1rf_lg11_w40_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rf_lg6_w22_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rf_lg8_w34_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib

export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1rf_lg11_w40_all.gds2 \
$(PLATFORM_DIR)/gds/gf12_1rf_lg6_w22_all.gds2 \
Expand All @@ -32,7 +32,6 @@ export CORE_AREA = 2 2 608 498
export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io.tcl

export PLACE_DENSITY_LB_ADDON = 0.05
export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl
#
export MACRO_PLACE_HALO = 7 7

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10 changes: 4 additions & 6 deletions flow/designs/gf12/tinyRocket/config.mk
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14,11 +14,11 @@ export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \

export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w32_all.lef \
$(PLATFORM_DIR)/lef/gf12_1rf_lg6_w32_byte.lef
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w32_all.lef \
$(PLATFORM_DIR)/lef/gf12_1rf_lg6_w32_byte.lef

export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rf_lg6_w32_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rf_lg6_w32_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/gf12_1rf_lg6_w32_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
$(PLATFORM_DIR)/lib/gf12_1rf_lg6_w32_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \

#$(PLATFORM_DIR)/lib/gf12_2rf_lg10_w32_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib

Expand All @@ -31,8 +31,6 @@ export CORE_AREA = 19.992 20.16 380.016 380.16

export PLACE_DENSITY = 0.20

export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl

ifeq ($(USE_FILL),1)
export DESIGN_TYPE = CELL
else
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