Tie Cells at FP Stage, Improved Cell Padding (#1226)

+ Added "logging to" information for long-running steps (CTS and Routing)
+ Added variable `GPL_CELL_PADDING` for global placement, with a default value of 0 (value divided by 2 and applied to both the left and right of the cell)
+ Add feature to also print mounted scripts' version if the container version does not match
+ Add `insert_tiecells` after floorplanning
~ `replace.tcl`, `opendp.tcl` -> `gpl.tcl`, `dpl.tcl`
~ `CELL_PAD` renamed `DPL_CELL_PADDING` for detailed placement, default value still 4, value divided by 2 and applied to both the left and right of the cell
~ DONT_BUFFER_PORTS given a default value (empty)
~ `remove_buffers` -> `remove_buffers_from_ports` (to more explicitly state what it does)
~ Renamed `RUN_ROUTING_DETAILED` to `RUN_DRT` (with translation behavior)
~ Cleanup OR antenna check
- Removed `CELL_PAD` from metrics and comparison
- Removed `widen_site_width`, `use_widened_lefs` and `use_original_lefs`: I don't know who used site widening
- Removed `MERGED_LEF_UNPADDED`: `MERGED_LEF` can be used for all places where the "unpadded" one was used

CONTRIBUTING.md

@@ -1,6 +1,5 @@
 # How to Contribute
-We'd love to accept your patches and contributions to this project. There are
-just a few small guidelines you need to follow.
+We'd love to accept your patches and contributions to this project. There are just a few small guidelines you need to follow.
 
 # Branching
 For various reasons, it's recommended to call working branches, even in your forks, something else other than `master` or `main`, as those two branch names do have some special behavior associated with them. 

configuration/README.md

@@ -14,6 +14,20 @@ This page describes user-configurable variables and their default values.
 
 These variables are optional that can be specified in the design configuration file.
 
+### General
+|Variable|Description|
+|-|-|
+| `PDK` | Specifies the process design kit (PDK). <br> (Default: `sky130A` )|
+| `STD_CELL_LIBRARY` | Specifies the standard cell library to be used under the specified PDK. <br> (Default: `sky130_fd_sc_hd` )|
+| `STD_CELL_LIBRARY_OPT` | Specifies the standard cell library to be used during resizer optimizations. <br> (Default: `$STD_CELL_LIBRARY` )|
+| `PDK_ROOT` | Specifies the folder path of the PDK. It searches for a `config.tcl` in `$PDK_ROOT/$PDK/libs.tech/openlane/` directory and at least have one standard cell library config defined in `$PDK_ROOT/$PDK/libs.tech/openlane/$STD_CELL_LIBRARY`. |
+| `DIODE_PADDING` | Diode cell padding; increases the width of diode cells during placement checks. <br> (Default: `2` microns -- 2 sites)|
+| `MERGED_LEF` | Points to `merged.lef`, which is a merger of various LEF files, including the technology lef, cells lef, any custom lefs, and IO lefs. |
+| `NO_SYNTH_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/no_synth.cells` and if it's not found, then the original liberty will be used as is. |
+| `DRC_EXCLUDE_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis and timing optimizations. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/drc_exclude.cells` and if it's not found, then the original liberty will be used as is. In other words, `DRC_EXCLUDE_CELL_LIST` contain the only excluded cell list in timing optimizations. |
+| `EXTRA_LEFS` | Specifies LEF files of pre-hardened macros to be merged in the design currently getting hardened |
+| `EXTRA_GDS_FILES` | Specifies GDS files of pre-hardened macros to be merged in the design currently getting hardened |
+
 ### Synthesis
 
 |Variable|Description|
@@ -132,6 +146,7 @@ These variables worked initially, but they were too sky130 specific and will be
 | `PL_MACRO_HALO` | Macro placement halo. Format: `{Horizontal} {Vertical}` <br> (Default: `0 0`um). |
 | `PL_MACRO_CHANNEL` | Channel widths between macros. Format: `{Horizontal} {Vertical}` <br> (Default: `0 0`um). |
 | `MACRO_PLACEMENT_CFG` | Specifies the path a file specifying how openlane should place certain macros |
+| `DONT_BUFFER_PORTS` | Semicolon;delimited list of nets from which to remove buffers after placement (but before resizing). <br> (Default: Empty) |
 
 ### CTS
 
@@ -187,9 +202,9 @@ These variables worked initially, but they were too sky130 specific and will be
 | `GLB_RT_MAXLAYER` | **Removed: Use RT_MAX_LAYER**: The number of highest layer to be used in routing. <br> (Default: `6`)|
 | `GLB_RT_CLOCK_MINLAYER` | **Removed: Use RT_CLOCK_MIN_LAYER**: The number of lowest layer to be used in routing the clock net. <br> (Default: `GLB_RT_MINLAYER`)|
 | `GLB_RT_CLOCK_MAXLAYER` | **Removed: Use RT_CLOCK_MIN_LAYER**: The number of highest layer to be used in routing the clock net. <br> (Default: `GLB_RT_MAXLAYER`)|
+| `GLB_RT_L{1/2/3/4/5/6}_ADJUSTMENT` | **Removed: See PDK variable `GLB_RT_LAYER_ADJUSTMENTS` instead**: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to a metal layer in sky130A. Values ranged from 0 to 1 |
 | `GLB_RT_UNIDIRECTIONAL` | **Removed**: Allow unidirectional routing. 0 = false, 1 = true <br> (Default: `1`) |
 | `GLB_RT_TILES` | **Removed**: The size of the GCELL used by Fastroute during global routing. <br> (Default: `15`) |
-| `GLB_RT_L{1/2/3/4/5/6}_ADJUSTMENT` | **Removed: See PDK variable `GLB_RT_LAYER_ADJUSTMENTS` instead**: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to a metal layer in sky130A. Values ranged from 0 to 1 |
 
 ### RC Extraction
 
@@ -224,32 +239,15 @@ These variables worked initially, but they were too sky130 specific and will be
 | `LVS_CONNECT_BY_LABEL` | Enables connections by label in LVS by skipping `extract unique` in magic extractions. <br> Default: `0` |
 | `YOSYS_REWRITE_VERILOG` | Enables yosys to rewrite the verilog before LVS producing a canonical verilog netlist with verbose wire declarations. This flag will be ignored if `LEC_ENABLE` is 1, and it will be rewritten anyways. 1 = Enabled, 0 = Disabled <br> (Default: `0` ) |
 
-### Misc
+### Flow control
 
 |Variable|Description|
 |-|-|
-| `PDK` | Specifies the process design kit (PDK). <br> (Default: `sky130A` )|
-| `STD_CELL_LIBRARY` | Specifies the standard cell library to be used under the specified PDK. <br> (Default: `sky130_fd_sc_hd` )|
-| `STD_CELL_LIBRARY_OPT` | Specifies the standard cell library to be used during resizer optimizations. <br> (Default: `$STD_CELL_LIBRARY` )|
-| `PDK_ROOT` | Specifies the folder path of the PDK. It searches for a `config.tcl` in `$PDK_ROOT/$PDK/libs.tech/openlane/` directory and at least have one standard cell library config defined in `$PDK_ROOT/$PDK/libs.tech/openlane/$STD_CELL_LIBRARY`. |
-| `CELL_PAD` | Cell padding; increases the width of cells. <br> (Default: `4` microns -- 4 sites)|
-| `DIODE_PADDING` | Diode cell padding; increases the width of diode cells during placement checks. <br> (Default: `2` microns -- 2 sites)|
-| `MERGED_LEF_UNPADDED` | Points to `merged_unpadded.lef` by default. it contains the technology LEF for the used STD_CELL_LIBRARY merged with the LEF file for all the cells. |
-| `MERGED_LEF` | points to `merged.lef`, which is `merged_unpadded.lef` but with cell padding. This is controlled by CELL_PAD. |
-| `NO_SYNTH_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/no_synth.cells` and if it's not found, then the original liberty will be used as is. |
-| `DRC_EXCLUDE_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis and timing optimizations. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/drc_exclude.cells` and if it's not found, then the original liberty will be used as is. In other words, `DRC_EXCLUDE_CELL_LIST` contain the only excluded cell list in timing optimizations. |
-| `EXTRA_LEFS` | Specifies LEF files of pre-hardened macros to be merged in the design currently getting hardened |
-| `EXTRA_GDS_FILES` | Specifies GDS files of pre-hardened macros to be merged in the design currently getting hardened |
 | `TEST_MISMATCHES` | Test for mismatches between the OpenLane tool versions and the current environment. `all` tests all mismatches. `tools` tests all except the PDK. `pdk` only tests the PDK. `none` disables the check.<br> (Default: `all`) |
 | `QUIT_ON_MISMATCHES` | Whether to halt the flow execution or not if mismatches are found. (Default: `1`) |
-
-### Flow control
-
-|Variable|Description|
-|-|-|
 | `USE_GPIO_PADS` | Decides whether or not to use the gpio pads in routing by merging their LEF file set in `::env(USE_GPIO_ROUTING_LEF)` and blackboxing their verilog modules set in `::env(GPIO_PADS_VERILOG)`. 1=Enabled, 0=Disabled. <br> (Default: `0`) |
 | `LEC_ENABLE` | Enables logic verification using yosys, for comparing each netlist at each stage of the flow with the previous netlist and verifying that they are logically equivalent. Warning: this will increase the runtime significantly. 1 = Enabled, 0 = Disabled <br> (Default: `0`)|
-| `RUN_ROUTING_DETAILED` | Enables detailed routing. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `RUN_DRT` | Enables detailed routing. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
 | `RUN_LVS` | Enables running LVS. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
 | `PRIMARY_SIGNOFF_TOOL` | Determines whether `magic` or `klayout` is the primary signoff tool. <br> (Default: `magic`) |
 | `RUN_MAGIC` | Enables running magic and GDSII streaming. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|

configuration/floorplan.tcl

@@ -12,6 +12,8 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+set ::env(DESIGN_IS_CORE) 1
+
 # Floorplan defaults
 set ::env(FP_SIZING) relative
 set ::env(FP_CORE_UTIL) 50
@@ -52,6 +54,4 @@ set ::env(FP_PDN_VERTICAL_HALO) $::env(FP_PDN_HORIZONTAL_HALO)
 set ::env(FP_TAP_HORIZONTAL_HALO) 10
 set ::env(FP_TAP_VERTICAL_HALO) $::env(FP_TAP_HORIZONTAL_HALO)
 set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) 1
-set ::env(FP_PDN_ENABLE_MACROS_GRID) 1 
-
-set ::env(DESIGN_IS_CORE) 1
+set ::env(FP_PDN_ENABLE_MACROS_GRID) 1

configuration/general.tcl

@@ -54,7 +54,7 @@ set ::env(MAGIC_CONVERT_DRC_TO_RDB) 1
 set ::env(KLAYOUT_XOR_GDS) 1
 set ::env(KLAYOUT_XOR_XML) 1
 
-set ::env(RUN_ROUTING_DETAILED) 1
+set ::env(RUN_DRT) 1
 set ::env(RUN_SIMPLE_CTS) 0
 set ::env(CLOCK_PERIOD) "10.0"
 set ::env(RUN_KLAYOUT) 1
@@ -67,9 +67,6 @@ set ::env(USE_ARC_ANTENNA_CHECK) 1
 set ::env(FILL_INSERTION) 1
 set ::env(TAP_DECAP_INSERTION) 1
 
-set ::env(WIDEN_SITE) 1
-set ::env(WIDEN_SITE_IS_FACTOR) 1
-
 set ::env(RUN_SPEF_EXTRACTION) 1
 set ::env(RUN_CVC) 1
 

configuration/placement.tcl

@@ -39,3 +39,4 @@ set ::env(PL_MAX_DISPLACEMENT_X) 500
 set ::env(PL_MAX_DISPLACEMENT_Y) 100
 set ::env(PL_MACRO_HALO) {0 0}
 set ::env(PL_MACRO_CHANNEL) {0 0}
+set ::env(DONT_BUFFER_PORTS) {}

designs/manual_macro_placement_test/config.json

@@ -10,7 +10,7 @@
     "BASE_SDC_FILE": "dir::base.sdc",
     "PL_TARGET_DENSITY": 0.35,
     "PL_BASIC_PLACEMENT": 1,
-    "CELL_PAD": 0,
+    "DPL_CELL_PADDING": 0,
     "CLOCK_PERIOD": 100,
     "CLOCK_PORT": "clk1 clk2",
     "CLOCK_TREE_SYNTH": false,

designs/spm/config.json

@@ -9,30 +9,22 @@
     "FP_PDN_HOFFSET": 7,
     "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
     "pdk::sky130A": {
+        "FP_CORE_UTIL": 45,
         "scl::sky130_fd_sc_hd": {
-            "CLOCK_PERIOD": 10,
-            "SYNTH_MAX_FANOUT": 5,
-            "FP_CORE_UTIL": 45
+            "CLOCK_PERIOD": 10
         },
         "scl::sky130_fd_sc_hdll": {
-            "CLOCK_PERIOD": 10,
-            "SYNTH_MAX_FANOUT": 5,
-            "FP_CORE_UTIL": 49
+            "CLOCK_PERIOD": 10
         },
         "scl::sky130_fd_sc_hs": {
-            "CLOCK_PERIOD": 10,
-            "SYNTH_MAX_FANOUT": 5,
-            "FP_CORE_UTIL": 49
+            "CLOCK_PERIOD": 8
         },
         "scl::sky130_fd_sc_ls": {
             "CLOCK_PERIOD": 10,
-            "SYNTH_MAX_FANOUT": 5,
-            "FP_CORE_UTIL": 49
+            "SYNTH_MAX_FANOUT": 5
         },
         "scl::sky130_fd_sc_ms": {
-            "CLOCK_PERIOD": 10,
-            "SYNTH_MAX_FANOUT": 5,
-            "FP_CORE_UTIL": 49
+            "CLOCK_PERIOD": 10
         }
     }
 }

docs/source/hardening_macros.md

@@ -147,7 +147,7 @@ However, you can enable that by setting `PL_RESIZER_OVERBUFFER` to `1` and then
 
 ### Detailed Placement:
 
-The only value to consider here is the `CELL_PAD` which is usually selected for each (PDK,STD_CELL_LIBRARY) and should mostly be left as is. However, typically for the skywater libraries the value should be 4~6.
+The only value to consider here is the `DPL_CELL_PADDING` which is usually selected for each (PDK,STD_CELL_LIBRARY) and should mostly be left as is. However, typically for the skywater libraries the value should be 4~6.
 
 You can read more about that [here][0].
 

docs/source/openlane_commands.md

@@ -20,7 +20,7 @@ Most of the following commands' implementation exists in this [file][0]
 | `set_netlist <netlist>`   | | Sets the current netlist used by the flow to `<netlist>` |
 |    | `[-lec]` | Runs logic verification for the new netlist against the previous netlist. <br> Optional flag.       |
 | `set_def <def>`   | | Sets the current def file used by the flow to `<def>` |
-| `prep_lefs`   | | prepares the used lef files by the flow. This process includes merging the techlef and cells lef, generated a merged.lef and a merged_unpadded.lef. Both to be used by different stages of the flow.|
+| `prep_lefs`   | | prepares the used lef files by the flow. This process includes merging the techlef and cells lef, generating a merged.lef.|
 | `trim_lib`   | | prepares a liberty file (i.e. `LIB_SYNTH`) by trimming the `NO_SYNTH_CELL_LIST` and `DRC_EXCLUDE_CELL_LIST` from another input liberty file (i.e. `$::env(LIB_SYNTH_COMPLETE)`). |
 |    | `[-output <lib_file>]` | The lib file to output the trimmed liberty into. <br> Default: `$::env(LIB_SYNTH)` <br> Optional flag. |
 |    | `[-input <lib_file>]` | The input liberty file to trim the cells from. <br> Default: `$::env(LIB_SYNTH_COMPLETE)` <br> Optional flag. |
@@ -52,9 +52,6 @@ Most of the following commands' implementation exists in this [file][0]
 |    | `[-spice_path <path>]` |  Changes the save path for the spice files to `<path>`. <br> The default is the `<run_path>` under the `<design_path>` specified by the `<run_tag>` and the processed `design` <br> Optional flag.|
 |    | `[-save_path <path>]` |  Changes the save path for the save path for all the types of files to `<path>`. <br> The default is the `<run_path>/results/final`.<br> Optional flag.|
 |    | `-tag <run_tag>` |  **Removed:** Specifies the `<run_tag>` from which the views were generated.|
-| `widen_site_width`   | | generates two new lef files (merged_wider.lef and merged_unpadded_wider.lef) with a widened site width based on the values of `WIDEN_SITE_IS_FACTOR` and `WIDEN_SITE`, more about those in the [configurations/readme.md][13].|
-| `use_widened_lefs`   | | Switches to using the lef files with the widened site width in the flow.|
-| `use_original_lefs`   | | Switches to using the normal lef files in the flow.|
 | `label_macro_pins `   | | Labels the pins of a given macro def according to the netlist for lvs.|
 |    | `-lef <lef_file>` |  LEF file needed to have a proper view of the netlist AND the input DEF.|
 |    | `-netlist_def <def_file>` |  DEF view of the design that has the connectivity information.|
@@ -240,13 +237,13 @@ Most of the following commands' implementation exists in this [file][8]
 |---------------|------------------------|-----------------------------------------|
 | `global_routing` | | Runs global routing  on the processed design The resulting file is under `/<run_path>/tmp/routing/` . |
 | `global_routing_fastroute` | | Runs global routing  on the processed design using the openroad app's fastroute. The resulting file is under `/<run_path>/tmp/routing/` . |
-| `detailed_routing` | | Runs detailed routing on the processed design using OpenROAD TritonRoute, or DRCU based onthe value of `DETAILED_ROUTER`. The resulting file is under `/<run_path>/results/routing/` . |
-| `detailed_routing_tritonroute` | | Runs detailed routing on the processed design using OpenROAD TritonRoute based on the value of `DETAILED_ROUTER`. The resulting file is under `/<run_path>/results/routing/` . |
+| `detailed_routing` | | Runs detailed routing on the processed design. The resulting file is under `/<run_path>/results/routing/` . |
+| `detailed_routing_tritonroute` | | Runs detailed routing on the processed design using OpenROAD TritonRoute. The resulting file is under `/<run_path>/results/routing/` . 
 | `apply_route_obs`| | Uses `GRT_OBS` to insert obstruction for each macro in order to prevent routing for each specified layer on each macro. Check `GRT_OBS` in the configurations documentation for more details.|
 | `add_route_obs`| | Uses `GRT_OBS` to call `apply_route_obs`, then calls `apply_route_obs` again to apply obstructions over the whole die area based on the value of `GRT_MAXLAYER` up to the highest available metal layer.|
 | `run_routing` | | Runs diode insertion based on the strategy, then adds the routing obstructions, followed by `global_routing`, then `ins_fill_cells`, `detailed_routing`, and finally SPEF extraction on the processed design. The resulting file is under `/<run_path>/results/routing/`. It also generates a pre_route netlist using yosys and stores the results under `/<run_path>/results/synthesis`, and it runs yosys logic verification if enabled. |
 | `global_routing_cugr` | | **Removed: Aliases global_routing_fastroute**: Runs global routing  on the processed design using cugr. The resulting file is under `/<run_path>/tmp/routing/` . |
-| `detailed_routing_drcu` | | **Removed: Aliases detailed_routing_tritonroute** Runs detailed routing on the processed design using DRCU. The resulting file is under `/<run_path>/results/routing/` . |
+| `detailed_routing_drcu` | | **Removed: Aliases detailed_routing_tritonroute**: Runs detailed routing on the processed design using DRCU. The resulting file is under `/<run_path>/results/routing/` . |
 
 ## Magic Commands
 

docs/source/pdk_structure.md

@@ -97,8 +97,9 @@ This section defines the necessary variables to configure a standard cell librar
 | `PL_LIB` | Points to the lib view used in time driven placement.  |
 | `FILL_CELL` | Defines the fill cell. Used in fill insertion. Can use a wild card to define a class of cells. Example `sky130_fd_sc_hd__fill_*` |
 | `DECAP_CELL` | Defines the decap cell used for fill insertion. Can use a wild card to define a class of cells. Example `sky130_fd_sc_hd__fill_*` |
-| `CELL_PAD` | Defines the number of sites to pad the cells lef views with. |
-| `CELL_PAD_EXCLUDE` | Defines the cells to exclude from padding. |
+| `GPL_CELL_PADDING` | Cell padding value (in sites) for global placement. Using this is not strictly recommended as you can simply use the density control for global placement. <br> (Example: `0`) |
+| `DPL_CELL_PADDING` | Defines the number of sites to pad the cells lef views with during detailed placement . The number will be integer divided by 2 and placed on both sides. <br> (Example: `4`) |
+| `CELL_PAD_EXCLUDE` | Defines the cells to exclude from padding for both detailed placement. |
 | `CTS_ROOT_BUFFER` | Defines the cell inserted at the root of the clock tree. Used in CTS. |
 | `ROOT_CLK_BUFFER` | Root clock buffer of the clock tree. <br> (Example: `sky130_fd_sc_hd__clkbuf_16`) |
 | `CLK_BUFFER` | Clock buffer used for inner nodes of the clock tree. <br> (Example: `sky130_fd_sc_hd__clkbuf_4`) |

flow.tcl

@@ -369,14 +369,23 @@ set flags {-interactive -it -drc -lvs -synth_explore -run_hooks}
 parse_key_args "flow.tcl" argv arg_values $options flags_map $flags -no_consume
 
 if {[catch {exec cat $::env(OPENLANE_ROOT)/install/installed_version} ::env(OPENLANE_VERSION)]} {
-    if {[catch {exec git --git-dir $::env(OPENLANE_ROOT)/.git rev-parse HEAD} ::env(OPENLANE_VERSION)]} {
-        if {[catch {exec cat /git_version} ::env(OPENLANE_VERSION)]} {
-            set ::env(OPENLANE_VERSION) "N/A"
+    if {[catch {exec cat /git_version} ::env(OPENLANE_VERSION)]} {
+        if {[catch {exec git --git-dir $::env(OPENLANE_ROOT)/.git rev-parse HEAD} ::env(OPENLANE_VERSION)]} {
+            set ::env(OPENLANE_VERSION) "UNKNOWN"
         }
     }
 }
 
+if {![catch {exec git --git-dir $::env(OPENLANE_ROOT)/.git rev-parse HEAD} ::env(OPENLANE_MOUNTED_SCRIPTS_VERSION)]} {
+    if { $::env(OPENLANE_VERSION) == $::env(OPENLANE_MOUNTED_SCRIPTS_VERSION)} {
+        unset ::env(OPENLANE_MOUNTED_SCRIPTS_VERSION)
+    }
+}
+
 puts "OpenLane $::env(OPENLANE_VERSION)"
+if { [info exists ::env(OPENLANE_MOUNTED_SCRIPTS_VERSION)] } {
+    puts "(with mounted scripts from $::env(OPENLANE_MOUNTED_SCRIPTS_VERSION))"
+}
 puts "All rights reserved. (c) 2020-2022 Efabless Corporation and contributors."
 puts "Available under the Apache License, version 2.0. See the LICENSE file for more details."
 puts ""