This repository contains the implementation of a Universal Asynchronous Receiver/Transmitter (UART) module on a Field-Programmable Gate Array (FPGA). This project was completed as part of the EN2111 - Electronic Circuit Design module at the Department of Electronic & Telecommunication Engineering, University of Moratuwa, Sri Lanka.
The objective of this project is to design, implement, and verify a UART module on an FPGA, enabling reliable asynchronous serial communication.
- 📡 Full UART protocol implementation
- 💻 FPGA-based design and simulation
- 🔬 Comprehensive testbench development
- 🛠️ RTL code for both transmitter and receiver
- 📊 ModelSim simulation and timing analysis
The project was completed in four main phases:
- Studied UART protocol: data framing, synchronization, baud rate settings
- Explored existing Verilog UART implementations
- Selected a design suited to project requirements
- Developed Verilog testbenches for UART modules
- Simulated various data patterns and baud rates
- Debugged using ModelSim
- Set up FPGA environment using Intel Quartus
- Integrated 7-segment display drive logic
- Verified functionality and synthesized design
- Mapped GPIO pins and generated bitstream
- Used oscilloscope to probe UART TX and RX lines
- Verified start bit, data bits, parity, stop bits
- Analyzed waveform timing and signal integrity
- FPGA development board (e.g., DE0 Nano)
- Oscilloscope (for hardware signal analysis)
- Intel Quartus (for RTL design & FPGA programming)
- ModelSim (for simulation and verification)
