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fix(svm): fixup some arithmetics in the interpreter #620

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@Rexicon226 Rexicon226 requested a review from dnut March 18, 2025 08:02
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codecov bot commented Mar 18, 2025

Codecov Report

Attention: Patch coverage is 97.29730% with 1 line in your changes missing coverage. Please review.

Files with missing lines Patch % Lines
src/vm/interpreter.zig 96.66% 1 Missing ⚠️
Files with missing lines Coverage Δ
src/vm/tests.zig 98.68% <100.00%> (+0.01%) ⬆️
src/vm/interpreter.zig 97.12% <96.66%> (-0.56%) ⬇️
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@Rexicon226 Rexicon226 force-pushed the Rexicon226/svm-conform branch from bf88f12 to 956f89a Compare March 18, 2025 13:52
Instruction.lsh => if (opcode.is64())
lhs << @truncate(rhs)
else
@as(u32, @truncate(lhs)) << @truncate(rhs),
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Above, there is this:

const lhs: u64 = if (opcode.is64()) lhs_large else @as(u32, @truncate(lhs_large));

So, isn't it already truncated? What does the additional truncate do?

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It provides a different result type to the shift amount truncate. Honestly I should re-design this code to be generic over the bitsize of the instruction, so that I don't need to represent 32-bits in a 64-bit value, and then reduce it at each place.

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Did that here: 24ae663

This turned out way nicer than I thought, I had the idea to do this when I was first writing this implementation, but for some reason didn't do it. It also caught a bug in the mul32 implementation :).

@Rexicon226 Rexicon226 force-pushed the Rexicon226/svm-conform branch from 24ae663 to 80263ac Compare March 18, 2025 23:54
@Rexicon226 Rexicon226 force-pushed the Rexicon226/svm-conform branch from 80263ac to 2f2f981 Compare March 19, 2025 02:10
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Rexicon226 commented Mar 19, 2025

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