Areaopt + other small changes #48

kavyasreedhar · 2020-07-10T23:12:37Z

Some cleanup...

deletes tba from LakeTop/strg_ub because it is used as a glorified pass through module currently
removes chaining signals from RWArbiter because it is purely combinational
some transpose buffer cleanup
default LakeTop runs with use_sram_stub = True so macro is not used by default (Keyi asked for that update)
deletes magma-output=verilog from all our tests because this is a deprecated option that can sometimes cause issues and is not needed to generate Verilog during tests (after talking with Lenny about other issues)

Use lakearea branch on garnet.

… not break garnet

…m 0 bc output_index the only var col pixels depends on now is always 0 if dim = 0

…tput valid is 0

… already set to 0

…utput will be high in dim 0 case

… is not maintained and not necessary for verilog generation

…ss again

… reference

…aopt

mbstrange2

LGTM

Kavya Sreedhar added 29 commits June 29, 2020 20:34

remove stride mult

f57f723

making tb height everwhere in code, param and config reg are there to…

0636b50

… not break garnet

eliminate vars based on height like input_index

c4626f6

col pixels no depend on tb height, get rid of col_pixels = 0 under di…

107cba3

…m 0 bc output_index the only var col pixels depends on now is always 0 if dim = 0

delete mask_valid var

9f02cf9

remove dim = 0 case from rdy to arbiter bc it doesn't matter since ou…

16dc3cc

…tput valid is 0

delete num_tb except from gen list

4f87ea3

deleting a lot of tba, just creating tb

926fae6

delete unused bits param in tb

76e2e9a

delete unused import

b66159d

getting rid of unnecessary bits

6443f2e

clean up

ccbb0a6

no need for dim = 0 case for curr out start since output index abs is…

1d2a3c9

… already set to 0

delete dim = 0 for index outer and index outer stride

bbf5c67

reorg input to tb code, delete dim = 0 for output valid since pause_o…

a45d55b

…utput will be high in dim 0 case

adding dim=0 unit tests for fw1 and fw4

6b757c9

delete magma_output=verilog from fault tester run and compile bc that…

bdcdbfd

… is not maintained and not necessary for verilog generation

comment out index outer stride

744a036

remove dim = 0 from valid_data

73ff862

pycodestyle test_tb, 419.64 tb area

d0b51da

delete passing mem_valid_data through rw_arbiter

05b1652

in process of deleting tba

4b0f7b0

formatting / naming

49b0481

fixing col pixels type (?)

63f3cd7

make col_pixels 1D and packed with no explicit array, garnet tests pa…

7cc1f27

…ss again

have top verilog generation not generate tsmc macro

3c9b4b9

restore orig tba file, add some dims = 0 in comments in tb for future…

289d433

… reference

Merge branch 'master' of https://github.com/StanfordAHA/lake into are…

6969af5

…aopt

pycodestyle

0175ce9

kavyasreedhar requested a review from mbstrange2 July 10, 2020 23:12

kavyasreedhar added 2 commits October 3, 2020 12:30

merge with master

25905c2

rw arbiter test

dcf458d

mbstrange2 approved these changes Oct 3, 2020

View reviewed changes

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Areaopt + other small changes #48

Areaopt + other small changes #48

kavyasreedhar commented Jul 10, 2020 •

edited

Loading

mbstrange2 left a comment

Areaopt + other small changes #48

Are you sure you want to change the base?

Areaopt + other small changes #48

Conversation

kavyasreedhar commented Jul 10, 2020 • edited Loading

mbstrange2 left a comment

Choose a reason for hiding this comment

kavyasreedhar commented Jul 10, 2020 •

edited

Loading