Question about VexRiscv Debug Interface and onChipRam Behavior in Murax on Arty-A7

[Usutatsu]

Hello everyone,
I'm currently experimenting with Murax (including the NativeJTAG feature) on a Xilinx Arty-A7 35T board, and I've successfully run a simple program on it.
I have a question regarding the debug interface of VexRiscv. My setup involves connecting the board to a Linux PC via USB, and I'm using OpenOCD and GDB for debugging.
When I load a .elf file in GDB, is the program data actually being stored in Murax's onChipRam?
If so, how is the data transferred to the onChipRam? Specifically, does VexRiscv execute load/store instructions to write the data into onChipRam based on what is provided by the SystemDebugger?
I would really appreciate any insights into the detailed behavior of this process. Thank you in advance!

[Dolu1990]

Hi,

When I load a .elf file in GDB, is the program data actually being stored in Murax's onChipRam?

Yes

If so, how is the data transferred to the onChipRam? Specifically, does VexRiscv execute load/store instructions to write the data into onChipRam based on what is provided by the SystemDebugger?

Yes, openocd will push instruction one by one for vexriscv to execute, so mostly load imediate + store instructions.
(The system debugger doesnt provide direct access to the memory, but mostly just an interface to push instruction to the vexriscv pipeline)

[Usutatsu]

Thank you for your response. It helped me deepen my understanding.
I have a follow-up question.
From your explanation, I understood that when I select a .elf file in GDB and execute the load command, the command is transmitted through OpenOCD → JTAG → SystemDebugger, and then via the debugBus, the VexRiscv core executes store instructions.
These instructions write the program's binary data (such as the .text section and .data section) into the onChipRam via the dBus.
Is my understanding correct that both the .text section (which includes instruction codes and immediate values) and the .data section (which includes initialized data) are written to onChipRam using store instructions in the same way?

Also, when stepping through the assembler code line by line in the GDB debugger, does the VexRiscv core actually fetch instructions from onChipRam in response to commands from the SystemDebugger?