#81 Update SpinalHDL / sbt

build.sbt

@@ -12,7 +12,8 @@ lazy val root = (project in file(".")).
 
     libraryDependencies ++= Seq(
       "org.scalatest" %% "scalatest" % "3.2.5",
-      "org.yaml" % "snakeyaml" % "1.8"
+      "org.yaml" % "snakeyaml" % "1.8",
+      "org.scalactic" %% "scalactic" % "3.2.10"
     ),
     name := "SaxonSoc",
     scalaSource in Compile := baseDirectory.value / "hardware" / "scala",

hardware/scala/saxon/Apb3DecoderStdGenerators.scala

@@ -192,12 +192,13 @@ case class Apb3PlicGenerator(apbOffset : Handle[BigInt] = Unset) (implicit decod
     val apb = Apb3(apbConfig)
     val bus = Apb3SlaveFactory(apb)
 
-    val targets = targetsModel.map(flag =>
+    val targets = targetsModel.zipWithIndex.map { case (flag, id) =>
       PlicTarget(
+        id = id,
         gateways = gateways.map(_.get),
         priorityWidth = priorityWidth
       ).setCompositeName(flag, "plic_target")
-    )
+    }
 
 //    gateways.foreach(_.priority := 1)
 //    targets.foreach(_.threshold := 0)

hardware/scala/saxon/VexRiscvClusterGenerator.scala

@@ -8,7 +8,7 @@ import spinal.lib.bus.misc.SizeMapping
 import spinal.lib.com.jtag.{JtagInstructionDebuggerGenerator, JtagTapDebuggerGenerator}
 import spinal.lib.com.jtag.xilinx.Bscane2BmbMasterGenerator
 import spinal.lib.com.jtag.altera.VJtag2BmbMasterGenerator
-import spinal.lib.cpu.riscv.debug.{DebugModule, DebugModuleParameter, DebugTransportModuleJtagTap, DebugTransportModuleParameter, DebugTransportModuleTunneled}
+import spinal.lib.cpu.riscv.debug.{DebugModule, DebugModuleCpuConfig, DebugModuleParameter, DebugTransportModuleJtagTap, DebugTransportModuleParameter, DebugTransportModuleTunneled}
 import spinal.lib.generator._
 import spinal.lib.misc.plic.PlicMapping
 import vexriscv.VexRiscvBmbGenerator
@@ -115,7 +115,11 @@ class VexRiscvClusterGenerator(cpuCount : Int, withSupervisor : Boolean = true,
           harts = cpuCount,
           progBufSize = 2,
           datacount   = XLEN/32,
-          xlens = List(XLEN)
+          hartsConfig = cores.map(c => DebugModuleCpuConfig(
+            xlen = XLEN,
+            flen = c.config.get.FLEN,
+            withFpuRegAccess = c.config.get.FLEN == 64
+          ))
         )
       )
       systemReset := dm.io.ndmreset

hardware/scala/saxon/board/digilent/ArtyA7SmpLinux.scala

@@ -587,6 +587,7 @@ object ArtyA7SmpLinuxSystemSim {
   import spinal.core.sim._
 
   def main(args: Array[String]): Unit = {
+    Handle.loadHandleAsync = true
 
     case class Config(trace : Boolean, bin : String)
     val parser = new scopt.OptionParser[Config]("SpinalCore") {
@@ -830,8 +831,8 @@ object ArtyA7SmpLinuxSystemSim {
 
       val images = "../buildroot-build/images/"
 
-      dut.top.phy.logic.loadBin(0x00F80000, images + "fw_jump.bin")
-      dut.top.phy.logic.loadBin(0x00E00000, images + "u-boot.bin")
+//      dut.top.phy.logic.loadBin(0x00F80000, images + "fw_jump.bin")
+//      dut.top.phy.logic.loadBin(0x00E00000, images + "u-boot.bin")
 //      dut.top.phy.logic.loadBin(0x00000000, images + "Image")
 //      dut.top.phy.logic.loadBin(0x00FF0000, images + "linux.dtb")
 //      dut.top.phy.logic.loadBin(0x00FFFFC0, images + "rootfs.cpio.uboot")
@@ -842,10 +843,10 @@ object ArtyA7SmpLinuxSystemSim {
 
 //        dut.top.phy.logic.loadBin(0x00F80000, "software/standalone/fpu/build/fpu.bin")
 //      dut.top.phy.logic.loadBin(0x00F80000, "software/standalone/test/aes/build/aes.bin")
-      //dut.phy.logic.loadBin(0x00F80000, "software/standalone/dhrystone/build/dhrystone.bin")
+      dut.top.phy.logic.loadBin(0x00F80000, "software/standalone/dhrystone/build/dhrystone.bin")
 //      dut.phy.logic.loadBin(0x00F80000, "software/standalone/timerAndGpioInterruptDemo/build/timerAndGpioInterruptDemo_spinal_sim.bin")
 //      dut.phy.logic.loadBin(0x00F80000, "software/standalone/freertosDemo/build/freertosDemo_spinal_sim.bin")
-      dut.top.phy.logic.loadBin(0x00F80000, "software/standalone/mmcmeConfig/build/mmcmeConfig.bin")
+//      dut.top.phy.logic.loadBin(0x00F80000, "software/standalone/mmcmeConfig/build/mmcmeConfig.bin")
       println("DRAM loading done")
     }
   }

hardware/scala/saxon/package.scala

@@ -1,5 +1,9 @@
 import spinal.core.SpinalConfig
+import spinal.core.fiber.Handle
 
 package object saxon {
-  def SpinalRtlConfig = SpinalConfig(targetDirectory = "hardware/netlist")
+  def SpinalRtlConfig = {
+    Handle.loadHandleAsync = true // For compatibility
+    SpinalConfig(targetDirectory = "hardware/netlist")
+  }
 }

project/build.properties

@@ -1 +1 @@
-sbt.version=1.4.7
+sbt.version=1.6.0