Skip to content

Commit 8bd17a1

Browse files
fix: PE will idle while weightAdr == 0
+ add weightAdr into account inside pe state machine
1 parent 13fd2ab commit 8bd17a1

File tree

1 file changed

+6
-2
lines changed

1 file changed

+6
-2
lines changed

dla/src/pe/ProcessingElement.scala

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,10 @@ class ProcessingElementPad(debug: Boolean) extends Module with MCRENFConfig with
161161
protected val mightWeightIdxIncWire: Bool = Wire(Bool())
162162
protected val mightInActReadFinish: Bool = Wire(Bool())
163163
mightInActReadFinish.suggestName("mightInActReadFinish")
164+
/** true while weightMatrixData = 0*/
164165
protected val mightWeightReadFinish: Bool = Wire(Bool())
166+
/** true while weightAdr = 0, then it should turn to read new inActAdr */
167+
protected val mightWeightMatrixFinish: Bool = Wire(Bool())
165168
protected val psDataSPadIdxWire: UInt = Wire(UInt(log2Ceil(pSumDataSPadSize).W))
166169
// InActSPad
167170
protected val inActAdrIndexWire: UInt = Wire(UInt(inActAdrIdxWidth.W))
@@ -321,6 +324,7 @@ class ProcessingElementPad(debug: Boolean) extends Module with MCRENFConfig with
321324
mightWeightIdxIncWire := weightAdrDataWire === (weightDataIndexWire + 1.U) || mightWeightReadFinish // or meet finish signal
322325
mightInActReadFinish := inActMatrixDataWire === 0.U && !inActDataSPadFirstReadReg
323326
mightWeightReadFinish := weightMatrixDataReg === 0.U && !weightDataSPadFirstRead
327+
mightWeightMatrixFinish := weightAdrDataWire === 0.U
324328
inActAdrSPadIdxIncWire := (padEqIA && mightInActZeroColumnWire) || (((padEqWA && mightWeightZeroColumnWire) ||
325329
(padEqWB && mightWeightIdxIncWire)) && mightInActIdxIncWire) || (mightInActReadFinish && sPad =/= 0.U)
326330
weightAdrSPadIdxIncWire := (padEqMpy || sPad === padWeightData1) && mightWeightZeroColumnWire // FIXME: should add a state
@@ -397,8 +401,8 @@ class ProcessingElementPad(debug: Boolean) extends Module with MCRENFConfig with
397401
when (mightInActReadFinish) {
398402
readFinish()
399403
} .otherwise { // then haven't done all the MAC operations
400-
when (mightWeightIdxIncWire) { // finished read current weight data Matrix column
401-
when (mightInActIdxIncWire) { // finished read current inAct data Matrix column
404+
when (mightWeightIdxIncWire || mightWeightMatrixFinish) { // finished read current weight data Matrix column
405+
when (mightInActIdxIncWire || mightWeightMatrixFinish) { // finished read current inAct data Matrix column
402406
nextSPadInActAdr()
403407
when (inActSPadZeroColumnReg) {
404408
inActSPadZeroColumnReg := false.B

0 commit comments

Comments
 (0)