feat&fix: use verilatorBEnd and wire@MemCtrl addr

+ change backend to verilator @ClusterGroup & PECluster test;
+ using wire instead of register to get new address @MemCtrl;

Author: SingularityKChen

dla/src/diplomatic/MemCtrl.scala

@@ -48,9 +48,9 @@ class EyerissMemCtrlModule()(implicit val p: EyerissMemCtrlParameters) extends M
   protected val inActStarAdrReg: UInt = RegInit(0.U(p.addressBits.W))
   protected val weightStarAdrReg: UInt = RegInit(0.U(p.addressBits.W))
   protected val pSumStarAdrReg: UInt = RegInit(0.U(p.addressBits.W))
-  protected val inActReqAdrReg: UInt = RegInit(0.U(p.addressBits.W))
-  protected val weightReqAdrReg: UInt = RegInit(0.U(p.addressBits.W))
-  protected val pSumReqAdrReg: UInt = RegInit(0.U(p.addressBits.W))
+  protected val inActReqAdrWire: UInt = Wire(UInt(p.addressBits.W))
+  protected val weightReqAdrWire: UInt = Wire(UInt(p.addressBits.W))
+  protected val pSumReqAdrWire: UInt = Wire(UInt(p.addressBits.W))
   protected val inActReqSizeReg: UInt = RegInit(0.U(p.inActSizeBits.W))
   inActReqSizeReg.suggestName("inActReqSizeReg")
   protected val weightReqSizeReg: UInt = RegInit(0.U(p.weightSizeBits.W))
@@ -85,19 +85,19 @@ class EyerissMemCtrlModule()(implicit val p: EyerissMemCtrlParameters) extends M
   inActReqAdrAcc := Mux(inActReqFinOnce && inActIdMapIO.finish, 0.U,
     Mux(inActIdMapIO.alloc.fire(), inActReqAdrAcc + inActReqSizeReg, inActReqAdrAcc)
   )
-  inActReqAdrReg := inActStarAdrReg + inActReqAdrAcc
+  inActReqAdrWire := inActStarAdrReg + inActReqAdrAcc
   weightReqAdrAcc := Mux(weightIdMapIO.finish, 0.U,
     Mux(weightIdMapIO.alloc.fire(), weightReqAdrAcc + weightReqSizeReg, weightReqAdrAcc)
   )
-  weightReqAdrReg := weightStarAdrReg + weightReqAdrAcc
+  weightReqAdrWire := weightStarAdrReg + weightReqAdrAcc
   pSumReqAdrAcc := Mux(pSumIdMapIO.finish, 0.U,
     Mux(pSumIdMapIO.alloc.fire(), pSumReqAdrAcc + pSumReqSizeReg, pSumReqAdrAcc)
   )
-  pSumReqAdrReg := pSumStarAdrReg + pSumReqAdrAcc
+  pSumReqAdrWire := pSumStarAdrReg + pSumReqAdrAcc
   /** connections of require address */
-  io.inActIO.address := inActReqAdrReg
-  io.weightIO.address := weightReqAdrReg
-  io.pSumIO.address := pSumReqAdrReg
+  io.inActIO.address := inActReqAdrWire
+  io.weightIO.address := weightReqAdrWire
+  io.pSumIO.address := pSumReqAdrWire
 }
 
 class EyerissIDMapGenIO(val sourceWidth: Int) extends Bundle {

dla/tests/src/clustertest/ClusterGroupSpecTest.scala

@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.tester._
 import chisel3.util.DecoupledIO
 import chisel3.tester.experimental.TestOptionBuilder._
-import chiseltest.internal.WriteVcdAnnotation
+import chiseltest.internal.{VerilatorBackendAnnotation, WriteVcdAnnotation}
 import dla.cluster._
 
 import scala.util.Random
@@ -24,7 +24,8 @@ class ClusterGroupSpecTest extends ClusterSpecTestBasic {
   }
   behavior of "test the spec of Cluster Group"
   it should "work well on Cluster Group Controller" in {
-    test (new ClusterGroupController(debug = true)).withAnnotations(Seq(WriteVcdAnnotation)) { theCGCtrl =>
+    test (new ClusterGroupController(debug = true))
+      .withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { theCGCtrl =>
       val theTop = theCGCtrl.io
       val theDebugIO = theTop.debugIO
       val theClock = theCGCtrl.clock
@@ -198,7 +199,9 @@ class ClusterGroupSpecTest extends ClusterSpecTestBasic {
   }
 
   it should "work well on reading and writing via inner SRAM" in {
-    test (new ClusterGroup(true)).withAnnotations(Seq(WriteVcdAnnotation)) { theCG =>
+    test (new ClusterGroup(true))
+      .withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation))
+      { theCG =>
       val theTop = theCG.io
       val theClock = theCG.clock
       def pokeData(pokeIO: DecoupledIO[UInt], pokeData: List[Int], prefix: String): Unit = {

dla/tests/src/clustertest/PEClusterSpecTest.scala

@@ -3,7 +3,7 @@ package dla.tests.clustertest
 import chisel3._
 import chisel3.tester._
 import chisel3.util.DecoupledIO
-import chiseltest.internal.WriteVcdAnnotation
+import chiseltest.internal.{VerilatorBackendAnnotation, WriteVcdAnnotation}
 import chisel3.tester.experimental.TestOptionBuilder._
 import dla.cluster._
 import dla.pe.StreamBitsIO
@@ -15,7 +15,9 @@ class PEClusterSpecTest extends ClusterSpecTestBasic {
   override val printLogDetails = false
   behavior of "test the spec of PE Cluster"
   it should "work well on PE inAct Controller" in {
-    test (new PEClusterInAct(debug = true)) { thePEAct =>
+    test (new PEClusterInAct(debug = true))
+      .withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation))
+      { thePEAct =>
       val theTopIO = thePEAct.io
       val theClock = thePEAct.clock
       val theTopToCtrlDataIO = theTopIO.inActToArrayData.inActIO // inActRouter number
@@ -98,7 +100,9 @@ class PEClusterSpecTest extends ClusterSpecTestBasic {
   }
 
   it should "work well on PE Cluster" in {
-    test (new PECluster(true)).withAnnotations(Seq(WriteVcdAnnotation)) { thePECluster =>
+    test (new PECluster(true))
+      .withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation))
+    { thePECluster =>
       val theTopIO = thePECluster.io
       val theClock = thePECluster.clock
       val theCtrlIO = theTopIO.ctrlPath