Generated clock liberty bug fix

[stanminlee]

Generated clock liberty fixes

One area of code is not covered at all when handling liberty defined macros, leads to no logging of data structure for generated clocks.

Therefore, created helper function and populated relevant areas

---

Important

Introduces makeGeneratedClocks in VerilogReader to handle generated clocks, improving code modularity by refactoring existing logic in makeModuleInstNetwork and makeLibertyInst.

• Behavior:
  • Adds makeGeneratedClocks function in VerilogReader to map clock pin paths to liberty cells for generated clocks.
  • Calls makeGeneratedClocks in makeModuleInstNetwork and makeLibertyInst to handle generated clocks.
• Code Refactoring:
  • Removes inline generated clock handling logic from makeLibertyInst and makeModuleInstNetwork.
• Misc:
  • Updates VerilogReader.hh to declare makeGeneratedClocks.

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[greptile-apps]

Greptile Overview

Greptile Summary

This PR refactors generated clock handling by extracting duplicated logic into a helper function makeGeneratedClocks and adding a missing call in makeModuleInstNetwork.

Key Changes:

• Created makeGeneratedClocks helper function that processes Liberty-defined generated clocks
• Added generated clock handling to makeModuleInstNetwork (previously missing)
• Maintained existing call in makeLibertyInst
• Fixed variable scoping: moved inst_path declaration inside loop to prevent incorrect path reuse across multiple generated clocks

Impact:

• Generated clocks from Liberty macros are now properly logged for module instances
• Eliminates code duplication between the two instantiation paths
• Improves correctness when multiple generated clocks exist per cell

Confidence Score: 4/5

• Safe to merge with minor documentation improvement recommended
• Code refactoring is well-executed with proper function extraction and improved variable scoping. The missing generated clock handling in makeModuleInstNetwork is now addressed. Only minor issue is missing function documentation per project standards.
• No files require special attention beyond adding the suggested function comment

Important Files Changed

Filename	Overview
verilog/VerilogReader.cc	Extracted generated clock handling logic into helper function and fixed variable scoping bug
verilog/VerilogReader.hh	Added helper function declaration for makeGeneratedClocks

Sequence Diagram

sequenceDiagram
    participant VR as VerilogReader
    participant Net as Network
    participant LC as LibertyCell
    
    alt Module Instance Path
        VR->>VR: makeModuleInstNetwork()
        VR->>Net: makeInstance(cell, name, parent)
        VR->>VR: makeGeneratedClocks(lib_cell, inst)
    else Liberty Instance Path
        VR->>VR: makeLibertyInst()
        VR->>Net: makeInstance(cell, name, parent)
        VR->>VR: makeGeneratedClocks(lib_cell, inst)
    end
    
    VR->>LC: generatedClocks()
    LC-->>VR: clock list
    
    loop for each GeneratedClock
        VR->>Net: pathName(inst)
        Net-->>VR: original_inst_path
        VR->>VR: strip top-level prefix
        VR->>LC: masterPin()
        LC-->>VR: pin name
        VR->>VR: construct pinPath
        VR->>Net: addGeneratedClockPinToCell(pinPath, lib_cell)
    end

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