dff

seqlogic/dff.v

@@ -3,7 +3,7 @@ input d,clk,rst;
 output q,qbar;
 reg q;
 assign qbar=~q;
-always @(posedge clk or negedge rst) begin
+always @(posedge clk) begin
     if(rst)
     q<=1'b0;
     else

seqlogic/dfftb.v

@@ -11,16 +11,17 @@ initial begin
 end
 initial begin
     rst=1'b1;
-    #5 rst=1'b0;
+    forever
+    #4 rst=~rst;
 end
 initial begin
     $dumpfile("dfftb.vcd");
     $dumpvars(0,dfftb);
     $monitor($time," D=%b, Reset=%b ,Q=%b , Qbar=%b",d,rst,q,qbar);
     #5  d=1'b0;
     #10 d=1'b1;
-    #15 d=1'b0;
-    #20 d=1'b0;
+    #15 d=1'b1;
+    #20 d=1'b1;
     #25 d=1'b0;
     #30 d=1'b1;
     #35 d=1'b0;

seqlogic/dfftb.vcd

@@ -1,5 +1,5 @@
 $date
-	Fri Jun 23 00:44:19 2023
+	Mon Oct 09 15:22:50 2023
 $end
 $version
 	Icarus Verilog
@@ -33,73 +33,139 @@ x$
 x"
 x!
 $end
+#4
+0%
 #5
 1!
 0"
 0$
-0%
 1#
+#8
+1%
 #10
 0#
+#12
+0%
 #15
 0!
 1"
 1#
 1$
+#16
+1%
 #20
+0%
 0#
+#24
+1%
 #25
+1!
+0"
 1#
+#28
+0%
 #30
 0#
-0$
+#32
+1%
 #35
-1!
-0"
 1#
+#36
+0%
 #40
+1%
 0#
+#44
+0%
 #45
+0!
+1"
 1#
+#48
+1%
 #50
 0#
+#52
+0%
 #55
 1#
+#56
+1%
 #60
+0%
 0#
+#64
+1%
 #65
+1!
+0"
 1#
+#68
+0%
 #70
 0#
+#72
+1%
 #75
 1#
+0$
+#76
+0%
 #80
+1%
 0#
+#84
+0%
 #85
 1#
+#88
+1%
 #90
 0#
+#92
+0%
 #95
 1#
+#96
+1%
 #100
+0%
 0#
+#104
+1%
 #105
-0!
-1"
 1#
 1$
+#108
+0%
 #110
 0#
+#112
+1%
 #115
 1#
+#116
+0%
 #120
+1%
 0#
+#124
+0%
 #125
+0!
+1"
 1#
+#128
+1%
 #130
 0#
+#132
+0%
 #135
 1#
+#136
+1%
 #140
+0%
 0#
 0$