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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| `include "fadderstr.v" | ||
| `timescale 1ns/1ns | ||
| module fadderstrtb; | ||
| reg a,b; | ||
| reg cin; | ||
| wire sum; | ||
| wire cout; | ||
| fadd DUT(a,b,cin,sum,cout); | ||
| initial | ||
| begin | ||
| $dumpfile("fadderstrtb.vcd"); | ||
| $dumpvars(0,fadderstrtb); | ||
| $monitor($time," A=%b B=%b Cin=%b Sum=%b Cout=%b",a,b,cin,sum,cout); | ||
| a=1'b0;b=1'b0;cin=1'b0; | ||
| forever begin | ||
| #5 a=a+1'b1; | ||
| #2 b=b+1'b1; | ||
| cin=~cin; | ||
| end | ||
| end | ||
| initial begin | ||
| #100; | ||
| $finish; | ||
| end | ||
| endmodule |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,215 @@ | ||
| $date | ||
| Mon Sep 11 19:34:31 2023 | ||
| $end | ||
| $version | ||
| Icarus Verilog | ||
| $end | ||
| $timescale | ||
| 1ns | ||
| $end | ||
| $scope module fadderstrtb $end | ||
| $var wire 1 ! sum $end | ||
| $var wire 1 " cout $end | ||
| $var reg 1 # a $end | ||
| $var reg 1 $ b $end | ||
| $var reg 1 % cin $end | ||
| $scope module DUT $end | ||
| $var wire 1 # a $end | ||
| $var wire 1 $ b $end | ||
| $var wire 1 % cin $end | ||
| $var wire 1 " cout $end | ||
| $var wire 1 ! sum $end | ||
| $var wire 1 & s1 $end | ||
| $var wire 1 ' c2 $end | ||
| $var wire 1 ( c1 $end | ||
| $scope module g1 $end | ||
| $var wire 1 # a $end | ||
| $var wire 1 $ b $end | ||
| $var wire 1 ( c $end | ||
| $var wire 1 & s $end | ||
| $upscope $end | ||
| $scope module g2 $end | ||
| $var wire 1 & a $end | ||
| $var wire 1 % b $end | ||
| $var wire 1 ' c $end | ||
| $var wire 1 ! s $end | ||
| $upscope $end | ||
| $upscope $end | ||
| $upscope $end | ||
| $enddefinitions $end | ||
| $comment Show the parameter values. $end | ||
| $dumpall | ||
| $end | ||
| #0 | ||
| $dumpvars | ||
| 0( | ||
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| $end | ||
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| #100 |