VLSI Verification Prep: 6-Week Sprint 🚀

This repository tracks my daily progress and hands-on projects as I prepare for entry-level VLSI Verification and Design roles. My background in C++ and Data Structures gives me a strong foundation in Object-Oriented Programming, which I am actively translating into hardware verification.

🎯 Objective

To master synthesizable Verilog RTL design and build a fully functional, layered SystemVerilog verification environment by July 31st.

📂 Repository Structure (In Progress)

• 01_Digital_Logic: FSMs, Setup/Hold timing analysis, and clock domain crossing concepts.
• 02_Verilog_RTL: Synthesizable hardware blocks (FIFOs, ALUs, Shift Registers).
• 03_SV_Concepts: SystemVerilog OOP, interfaces, constrained randomization, and coverage.
• 04_Anchor_Project: A complete layered testbench (Generator, Driver, Monitor, Scoreboard) for a Synchronous FIFO.

🛠️ Tools Used

• Languages: Verilog (IEEE 1364), SystemVerilog (IEEE 1800)
• Simulator: EDA Playground (Synopsys VCS / Aldec Riviera-PRO)