target: cortex-m: defer cache identification on Cortex-M7 under reset

On Cortex-M7 only, several registers in System Control Space (SCS)
are not accessible when the CPU is under reset, generating a bus
error.
This cause OpenOCD to fail examining the CPU when the board reset
button is pressed or when the flag 'connect_assert_srst' is used
on 'reset_config' command.

Introduce a deferred identification of the cache and run it during
polling and at target halted (just in case of polling disabled).

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Ahmed HAOUES <ahmed.haoues@st.com>

flash/bluenrg-x: fallback to programming w/o loader

Signed-off-by: Tarek BOUCHKATI <tarek.bouchkati@st.com>

flash/stm32l4x: Support STM32WBA6x Devices

Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Tested-by: Tarek BOCHKATI <tarek.bouchkati@st.com>

flash/stm32l4x: support STM32C05/C09xx devices

Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>

server: gdb: respect command gdb_report_register_access_error

Commit 236c54c ("server/gdb_server.c: support unavailable
registers") correctly returns a string of 'x' when the register is
not available in the current target.

While implementing this, it incorrectly drops the pre-existing
feature of optionally ignoring errors while reading a register.

Re-add the check on 'gdb_report_register_access_error' to keep the
pre-existing behavior when a register error has to be ignored:
- return a string of '0';
- drop a debug message.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 236c54c ("server/gdb_server.c: support unavailable registers")

flash/stm32h5: add product state transition (Open to Close or Locked)

add all possible transition for STM32 product state for H5:
* Open to Provisioning
* Write key in OBK area using RSS_Lib function.
* Provisioning to TZclosed.
* Provisioning or TZclosed to Closed or Locked.

Signed-off-by: bouzazif <fedi.bouzazi@st.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@st.com>

flash/stldr: enhance write time

Use the available workarea size to program the written image.

Signed-off-by: bouzazif <fedi.bouzazi@st.com>
Change-Id: I83ccd98945c2103b0be52eb5b59a57380594abaf
Reviewed-by: Laurent LEMELE <laurent.lemele@st.com>

target/cortex_m: fix soft_reset_halt

in GDB event "gdb-flash-erase-start", a soft reset dont perform correctly target need to halt
Unfortunately, the execution of soft reset fails with time out error
(after 100 ms: S_HALT not raised => Target not halted  => reset not performed).
After investigation, Accordingly to ARM DDI0403E.B, chapter “B3.2.6 Application Interrupt and Reset Control Register,
AIRCR” before setting DEMCR.VC_CORERESET to perform local system reset,
we must halt the core otherwisethe behavior is unpredictable.

Change-Id: I440c66dca5effa2079ae330a31e2311525539e29
Signed-off-by: fedi BOUZAZI <fedi.bouzazi@st.com>

The openocd-0.12.0 release.

doc: fix semihosting_redirect command documentation

Change-Id: I78c82a21e4160851a5c0b58394ac7897479808ff
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>