Name		Name	Last commit message	Last commit date
Latest commit History 60 Commits
.vscode		.vscode
constr		constr
nvboard		nvboard
rom		rom
sim		sim
src		src
tools		tools
.gdbinit		.gdbinit
.gitignore		.gitignore
Makefile		Makefile
README.md		README.md

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rock-processor-core

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RISC-V CPU Core by verilog

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