This repository contains the code and documentation for Lab 7 of the E155 course. This lab focuses on hardware accelerated 128-bit AES encryption using Intel's AES-NI instruction set. It uses both the FPGA and MCU to excecute the AES encryption algorithm. FPGA handles enctryption while the MCU handles keywords, activation, and encryption keys. The two communicate via SPI with connections configured on the development board.
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FPGA and MCU Code For Implementing Hardware-Accelerated 128-bit AES encryption
Rex-Josaphat/E155-LAB7
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FPGA and MCU Code For Implementing Hardware-Accelerated 128-bit AES encryption
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