Swift Intrinsics

Unlock SIMD intrinsics.

Table of Contents

• Extensions
• Supported CPU flags
  • x86
  • ARM
  • RISC-V
• How to define CPU flags
  • Examples

Extensions

This library adds extensions to the existing Swift SIMD<N> types that use the supported intrinsics.

Some additional extensions are added for convenience without needing to declare CPU flags, including:

• Bit shift SIMD types
• Integer initialization from SIMD

Supported CPU flags

Format: CPU Flag (-Xcc -m<value> | -Xswiftc -D<value>)

x86

x86 cpu flags

• AES (aes | AES)
• AVX (avx | AVX)
• AVX2 (avx2 | AVX2)
• AVX512 (avx512 | AVX512)
• MMX (mmx | MMX)
• SHA (sha | SHA)
• SM3 (sm3 | SM3)
• SM4 (sm4 | SM4)
• SSE (sse | SSE)
• SSE2 (sse2 | SSE2)
• SSE3 (sse3 | SSE3)
• SSE4.1 (sse4.1 | SSE4_1)
• SSE4.2 (sse4.2 | SSE4_2)
• SSSE3 (ssse3 | SSSE3)

ARM

coming soon...

RISC-V

coming soon...

How to define CPU flags

Both -Xcc and -Xswiftc are required to compile correctly. It is recommended to use a script with your defined flags for developing a project utilizing this library. This is unavoidable with the current state of Swift.

• swift <build | run | test> -Xcc -m<flag1> -Xswiftc -D<flag1> -Xcc -m<flag2> -Xswiftc -D<flag2> -Xcc -m<flagN> -Xswiftc -D<flagN>

Examples

• SSE4.1 and AVX: swift build -Xcc -msse4.1 -Xswiftc -DSSE4_1 -Xcc -mavx -Xswiftc -DAVX
• AVX2: swift run -Xcc -mavx2 -Xswiftc -DAVX2
• SHA: swift test -Xcc -msha -Xswiftc -DSHA