Add support for attiny88

Cargo.toml

@@ -21,6 +21,7 @@ members = [
     "chips/atmega328p-hal",
     "chips/atmega32u4-hal",
     "chips/attiny85-hal",
+    "chips/attiny88-hal",
 
     # The board crates
     "boards/arduino-leonardo",

README.md

@@ -122,6 +122,9 @@ The chip-HAL crates currently support the following peripherals:
 * [`attiny85-hal`](./chips/attiny85-hal)
   - [x] Spinning Delay
   - [x] `PORTB` as digital IO (v2)
+* [`attiny88-hal`](./chips/attiny88-hal)
+  - [x] Spinning Delay
+  - [x] `PORTA`, `PORTB`, `PORTC`, `PORTD` as digital IO
 
 ### Supported Hardware
 In `boards/` there are crates for the following hardware.  Please note that this project is in no way affiliated with any of the vendors.

chips/attiny88-hal/Cargo.toml

@@ -0,0 +1,15 @@
+[package]
+name = "attiny88-hal"
+version = "0.1.0"
+authors = ["Andrew Dona-Couch <avr-hal@couchand.com>"]
+edition = "2018"
+
+[features]
+rt = ["avr-device/rt"]
+
+[dependencies]
+avr-hal-generic = { path = "../../avr-hal-generic/" }
+
+[dependencies.avr-device]
+version = "0.2.0"
+features = ["attiny88"]

chips/attiny88-hal/avr-attiny88.json

@@ -0,0 +1,31 @@
+{
+  "llvm-target": "avr-unknown-unknown",
+  "cpu": "attiny88",
+  "target-endian": "little",
+  "target-pointer-width": "16",
+  "target-c-int-width": "16",
+  "os": "unknown",
+  "target-env": "",
+  "target-vendor": "unknown",
+  "arch": "avr",
+  "data-layout": "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8",
+
+  "executables": true,
+
+  "linker": "avr-gcc",
+  "linker-flavor": "gcc",
+  "pre-link-args": {
+    "gcc": ["-Os", "-mmcu=attiny88"]
+  },
+  "exe-suffix": ".elf",
+  "post-link-args": {
+    "gcc": ["-Wl,--gc-sections"]
+  },
+
+  "singlethread": false,
+  "no-builtins": false,
+
+  "no-default-libraries": false,
+
+  "eh-frame-header": false
+}

chips/attiny88-hal/src/lib.rs

@@ -0,0 +1,18 @@
+#![no_std]
+
+extern crate avr_hal_generic as avr_hal;
+
+pub use avr_device::attiny88;
+/// See [`avr_device::entry`](https://docs.rs/avr-device/latest/avr_device/attr.entry.html).
+#[cfg(feature = "rt")]
+pub use avr_device::entry;
+
+pub use avr_hal::clock;
+pub use avr_hal::delay;
+
+pub mod port;
+
+pub mod prelude {
+    pub use crate::avr_hal::prelude::*;
+    pub use crate::port::PortExt as _;
+}

chips/attiny88-hal/src/port.rs

@@ -0,0 +1,98 @@
+pub trait PortExt {
+    type Parts;
+
+    fn split(self) -> Self::Parts;
+}
+
+avr_hal::impl_generic_pin! {
+    pub enum Pin {
+        A(crate::attiny88::PORTA, porta, pina),
+        B(crate::attiny88::PORTB, portb, pinb),
+        C(crate::attiny88::PORTC, portc, pinc),
+        D(crate::attiny88::PORTD, portd, pind),
+    }
+}
+
+avr_hal::impl_port! {
+    pub mod porta {
+        #[port_ext]
+        use super::PortExt;
+
+        #[generic_pin]
+        use Pin::A;
+
+        impl PortExt for crate::attiny88::PORTA {
+            regs: (pina, ddra, porta),
+            pa0: (PA0, 0),
+            pa1: (PA1, 1),
+            pa2: (PA2, 2),
+            pa3: (PA3, 3),
+        }
+    }
+}
+
+avr_hal::impl_port! {
+    pub mod portb {
+        #[port_ext]
+        use super::PortExt;
+
+        #[generic_pin]
+        use Pin::B;
+
+        impl PortExt for crate::attiny88::PORTB {
+            regs: (pinb, ddrb, portb),
+            pb0: (PB0, 0),
+            pb1: (PB1, 1),
+            pb2: (PB2, 2),
+            pb3: (PB3, 3),
+            pb4: (PB4, 4),
+            pb5: (PB5, 5),
+            pb6: (PB6, 6),
+            pb7: (PB7, 7),
+        }
+    }
+}
+
+avr_hal::impl_port! {
+    pub mod portc {
+        #[port_ext]
+        use super::PortExt;
+
+        #[generic_pin]
+        use Pin::C;
+
+        impl PortExt for crate::attiny88::PORTC {
+            regs: (pinc, ddrc, portc),
+            pc0: (PC0, 0),
+            pc1: (PC1, 1),
+            pc2: (PC2, 2),
+            pc3: (PC3, 3),
+            pc4: (PC4, 4),
+            pc5: (PC5, 5),
+            pc6: (PC6, 6),
+            pc7: (PC7, 7),
+        }
+    }
+}
+
+avr_hal::impl_port! {
+    pub mod portd {
+        #[port_ext]
+        use super::PortExt;
+
+        #[generic_pin]
+        use Pin::D;
+
+        impl PortExt for crate::attiny88::PORTD {
+            regs: (pind, ddrd, portd),
+            pd0: (PD0, 0),
+            pd1: (PD1, 1),
+            pd2: (PD2, 2),
+            pd3: (PD3, 3),
+            pd4: (PD4, 4),
+            pd5: (PD5, 5),
+            pd6: (PD6, 6),
+            pd7: (PD7, 7),
+        }
+    }
+}