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Welcome to the opae-xilinx wiki!

OPAE was released by Intel in 2017.

The Open Programmable Acceleration Engine (OPAE) Technology, included as part of the common developer interface between the Intel Xeon processor and an accelerator, is open code that improves developer productivity with a lightweight, consistent API across FPGA accelerator generations and platforms. Intel made this capability open to support a strong developer ecosystem for Intel Xeon processors with FPGA acceleration. The hardware-specific FPGA resource details are abstracted from the application developer, letting them focus on accelerating their workload instead of figuring out how to communicate with the FPGA. As part of this announcement, Intel has released OPAE on GitHub. Open sourcing the technology will help foster an open ecosystem and encourage the use of FPGA acceleration in the data center.

Since then, there have been requests for porting OPAE to Xilinx FPGA devices.

While studying the OPAE SDK, I realized that it is not only possible to port OPAE to Xilinx FPGA devices, but also important to make OPAE a cross-vendor platform which can abstract away the vendor specific features of FPGA devices. Targeting the Data Center market and facilitating the adoption of FPGA devices, Intel and Xilinx provide equivalent FPGA device technologies and low level software drivers. Traditionally, those technologies and drivers form a barrier, preventing acceleration applications and accelerator logic designs from migrating freely among FPGA device vendors. However, based on what has been well documented by OPAE and XRT, a further unified SW API and a more commonly used HW interface will provide both SW and HW developers with an opportunity to write programs and accelerators that can be deployed across FPGA devices and vendors.

The "opae-xilinx" project is an attempt to make OPAE vendor neutral.

The project will be carried on along the following steps:

1. Emulate the FIU and AFU interface with a Xilinx FPGA PCIe development board.
2. Playing with the OPAE-driver on a virtual FPGA card in the QEMU environment.
3. Emulate the FME interface by modifying the OPAE-SDK to use Xilinx tools for PR and Thermal.
4. Modify the OPAE-SDK for a set of vendor-neutral SW APIs and HW interfaces.