HGA101 is a crude GPGPUdesign, with a 5-stage RISC-V32ia core and a 16bit*8lane integer/half-precision float SIMD pipeline.

this is a part of the RV-AT project (https://github.com/RV-AT)

Now everything is WIP

Please bare this in mind: THIS IS AN EXPERIMENTAL DESIGN AND I DO NOT PROVIDE ANY GUARANTEE

Some more info and thank will be added here after FPGAChina 2020 competetion finished, and I will keep working on this project

Now status:

Code Core done, SoC Not started

Testbench Module level TB WIP , Core TB not started

Hardware Not started

Scripts Test and elaborate suite WIP