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cpu/samd21: optimized pin config for PWM driver #4137

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merged 5 commits into from
Nov 5, 2015

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haukepetersen
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@haukepetersen haukepetersen added Type: enhancement The issue suggests enhanceable parts / The PR enhances parts of the codebase / documentation Platform: ARM Platform: This PR/issue effects ARM-based platforms Impact: minor The PR is small in size and might only require a quick look of a knowledgeable reviewer labels Oct 22, 2015
@haukepetersen haukepetersen added this to the Release NEXT MAJOR milestone Oct 22, 2015
@PeterKietzmann
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The change looks reasonable to me on the first sight. @A-Paul do you have capacities to have a quick look at the code and the pwm output signal?

@@ -160,15 +159,15 @@ static const pwm_conf_t pwm_config[] = {
#if PWM_0_EN
{TCC1, {
/* port , pin, AF, chan */
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Isn't it more precise like this?
/* (port, pin), AF, chan */

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yepp, forgot to adjust the comment...

@A-Paul
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A-Paul commented Oct 22, 2015

Tested with board.
All four channel work. But:
2015-10-22 20:42:54,803 - INFO # requested: 1000 Hz, got 750 Hz
Real frequency on output is ~746Hz.

@haukepetersen
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the freq issue is unrelated to this PR. I will look into it and open another one to address that issue...

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@A-Paul if you agree, please give you ACK, set the"Ready for CI build" label and restart Travis. If he agrees as well, hit the merge button.

/* port , pin, AF, chan */
{(PortGroup *)0x41004400, 6, 4, 0},
{(PortGroup *)0x41004400, 7, 4, 1}
/* GPIO pin, MUX value, TCC channel */
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Why just three now?

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read the code...

Because the driver is now making use of the gpio_init_mux function...

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I asked because i saw four parameters in the following expression:
{GPIO_PIN(PA, 6), GPIO_MUX_E, 0},
and the comment might explain what to put in here.

And not because I didn't read the code.

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ups, the first comment came out wrong (now that I read it again), didn't mean to offend...

I see by the changed paradigm of defining GPIOs (former: gpio port + gpio pin, now only gpio pin, combining both port+pin) that the comment above should be quite sufficient. So whenever talking about GPIO pin, it is IMHO clear, what is meant, right?

@A-Paul A-Paul added the CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR label Oct 26, 2015
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A-Paul commented Nov 5, 2015

@haukepetersen, sorry for being to ambitious with asking for compliance with coding conventions or documentation.
Travis seems happy so far.

A-Paul pushed a commit that referenced this pull request Nov 5, 2015
cpu/samd21: optimized pin config for PWM driver
@A-Paul A-Paul merged commit bf63e09 into RIOT-OS:master Nov 5, 2015
@haukepetersen haukepetersen deleted the opt_samr21_pwm branch November 9, 2015 10:07
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