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drivers/ws281x: add SysTick + GPIO LL backend #20646
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drivers/ws281x: add SysTick + GPIO LL backend #20646
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Check warning on line 63 in drivers/ws281x/systick_gpio_ll.c
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Check warning on line 65 in drivers/ws281x/systick_gpio_ll.c
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For 48 MHz this is:
(325 - 50) * 48 * 10^6 / 10^9 = 13.2
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so 13 cyles for one wait ( which has (a load, a compare and a jump back if bit 16 isn't set) i think this is plenty of time to do this multiple times.
the short wait (300ns) has exact the same number of wait as with your code but it does not do a setup in the low period but does just three short waits instead.
i thought you where talking about 13cycle for the 1 µsecond
Check warning on line 69 in drivers/ws281x/systick_gpio_ll.c
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ahh i see where something precise is need (high time) there are only: set; wait and clr. and for the low time the inprecise start; wait; and the next start is placed
instead of reconfiguring the systick each time; i would start the systick once configured to some interval that cover high and low and wait for the count flag to raise to raise n times.
eg.:
this probably makes the whole thing less jittery
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That adds a branch in the timing sensitive phase and waiting for 300 ns on a STM32F072 is already pretty challenging with one time starting the systick timer. I doubt that you can start the systick timer three times within that time budget.
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not starting you just have it running and wait for n ticks
this is much faster then what you are currently doing ( and also kindof dumber (a little more the stupid of KISS)
maybe the c version in the next comment clears this up
the 3 and the 6 where guess numbers looking at the manual it is
300ns
or 400 ns
(ws2512b version 2 but it seems that that should also work with most valid v1 timings)
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the manuals that i found that had tolerances with the highs an lows would also be fine with the 300 ns and the 1: 2/3 1/3 and 0: 2/3 1/3 ( going close to the tolerances)
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What was the argument to split a single wait into three?
In any case: Each of the three waits would have to spin until a flag is set, clear the flag, and spin again. On the
nucleo-f072rb
the total wait is 13 cycles. Splitting that into three waits means 4 CPU cycles per wait. That is not possible to implement.There was a problem hiding this comment.
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https://godbolt.org/z/4nn3a3e7n
see function t2 the wait loop has 2 instructions
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Yeah, but a conditional branch will take more than one CPU cycle.
And again: Why divide a single wait? It adds lines or code, bytes to
.text
. And why into three waits? Wouldn't 42 or 1337 be much better numbers?There was a problem hiding this comment.
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because the has timing that are 1/4:3/4 or 1/3:2/3
you can put the branch outside of the time critical path
when i wrote the first suggestion i wasn't aware that we run the nucleo 72 @ 12MHz (I am still not sure but 13 cycles in about a microseconds would fit 12MHz)
but the reconfiguration of the systick is at least 7 instructions (if the register adresses are loaded) and a wait of unknown length
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it about not reconfiguring the systimer
this spreads the waits a little better so that they each have least amount of empty loops
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lets try to rewrite my pseudo code in pseudo c
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and then there is the potential use of the systick irq
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The overhead of entering the IRQ, backing up the state etc. takes way longer than the total time budget
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ok the irq thing might not be the right choice if you got 4 cycles