cpu/avr8_common: Prepare for rework ISR #19777
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Code looks good to me, but the CI has some comments. Note: The vera++ annotations are completely unrelated to this PR and #19779 should fix them. |
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The avr8_state store state information used to determine scheduling and uart irq. This move all uart irq states to avr8_state_uart variable. It introduce the use of General Purpose IO Register 0 (GPIOR0) when available and now all uarts from xmega can be used. This is a preparation for future scheduling and irq optimizations. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The avr8_state variable uses bit operation to set/clear the state. This rework avr8_state to use increment/decrement instead. It introduce the use of General Purpose IO Register 1 (GPIOR1) when available. This is a preparation for future scheduling and irq optimizations. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The thread_yield_higher is a normal functions. However it has a non regular return instruction which is useless. This remove the useless return on thread_yield_higher to save flash bytes. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
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The current ISR implementation for AVR8 requires use of avr8_[enter/exit]_isr pair which add some boilerplate on code. This add AVR8_ISR which clean-up the code and make it simpler and hides any schedule detail from the user perspective. This is a preparation for future scheduling and irq optimizations. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
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Jul 11, 2023
19777: cpu/avr8_common: Prepare for rework ISR r=benpicco a=nandojve ### Contribution description This prepares for rework how ISR is handled for AVR-8 platform. It is not expected changes on the behavior but tests on other boards were welcome to avoid regressions. #### Improvements * Split UART state from ISR states. Now it is necessary two variables and GPIORx registers are automatically selected when available. * UART states now supports up to 8 UARTs. * Added AVR8_ISR macro do clean-up and hide internals related to ISR processing. This allows changes on ISR without any other changes on drivers. ### Testing procedure Tests were conducted using atmega328p-xplained-mini and atxmega-a1u-xpro and the zigduino board was only built. The example thread_duel was used to test regressions. 19798: cpu/nrf53: add I2C and SPI support r=benpicco a=dylad ### Contribution description This PR provides support for nRF53 SPI and I2C. It also moves common structs from each nRF CPU folder to `cpu/nrf5x_common` to avoid duplication. Moreover, since nRF9160 and nRF5340 have shared IRQ for UART/SPI/I2C. Both this families now use a common file to register and manage these interrupts. Note that nRF9160 have different name for its interrupts than nRF5340 but they have the same purpose. ### Testing procedure Since some structs were moved around, I think this PR should be carefully tested against nRF52, nRF53 and nRF9160 to avoid any issues. On nRF5340DK-APP, SPI can be tested with its onboard SPI flash. ### Issues/PRs references Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com> Co-authored-by: Dylan Laduranty <dylan.laduranty@mesotic.com>
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Contribution description
This prepares for rework how ISR is handled for AVR-8 platform. It is not expected changes on the behavior but tests on other boards were welcome to avoid regressions.
Improvements
Testing procedure
Tests were conducted using atmega328p-xplained-mini and atxmega-a1u-xpro and the zigduino board was only built. The example thread_duel was used to test regressions.