cpu/stm32/gpio_all: fix IRQ handler for G0/L5/MP1 families #16319
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
jue89
added
Type: bug
jue89
requested review from
aabadie,
DipSwitch,
fjmolinas and
vincent-d
as code owners
jue89
added
the
CI: ready for build
benpicco
approved these changes
May 23, 2021
|
Thanks for your review! |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Contribution description
This is a follow-up for #16272 for the STM32G0, STM32L5 and STM32MP1 families. The same description applies.
The reference manuals I based this PR on:
Testing procedure
I don't own a board with a CPU of the mentioned families. If you do: please verify that GPIO IRQs are still working.
tests/periph_gpioshould be a suitable application.Issues/PRs references
#16272