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Merge pull request #17827 from aabadie/pr/board/nucleo-f439zi
boards: add support for nucleo-f439zi
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# Copyright (c) 2022 Inria | ||
# | ||
# This file is subject to the terms and conditions of the GNU Lesser | ||
# General Public License v2.1. See the file LICENSE in the top level | ||
# directory for more details. | ||
# | ||
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config BOARD | ||
default "nucleo-f439zi" if BOARD_NUCLEO_F439ZI | ||
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config BOARD_NUCLEO_F439ZI | ||
bool | ||
default y | ||
select BOARD_COMMON_NUCLEO144 | ||
select CPU_MODEL_STM32F439ZI | ||
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# Put defined MCU peripherals here (in alphabetical order) | ||
select HAS_PERIPH_DMA | ||
select HAS_PERIPH_ETH | ||
select HAS_PERIPH_I2C | ||
select HAS_PERIPH_PWM | ||
select HAS_PERIPH_RTC | ||
select HAS_PERIPH_SPI | ||
select HAS_PERIPH_TIMER | ||
select HAS_PERIPH_UART | ||
select HAS_PERIPH_USBDEV | ||
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source "$(RIOTBOARD)/common/nucleo144/Kconfig" |
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MODULE = board | ||
DIRS = $(RIOTBOARD)/common/nucleo | ||
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include $(RIOTBASE)/Makefile.base |
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ifneq (,$(filter netdev_default,$(USEMODULE))) | ||
USEMODULE += stm32_eth | ||
endif | ||
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include $(RIOTBOARD)/common/nucleo/Makefile.dep |
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CPU = stm32 | ||
CPU_MODEL = stm32f439zi | ||
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# Put defined MCU peripherals here (in alphabetical order) | ||
FEATURES_PROVIDED += periph_dma | ||
FEATURES_PROVIDED += periph_eth | ||
FEATURES_PROVIDED += periph_i2c | ||
FEATURES_PROVIDED += periph_pwm | ||
FEATURES_PROVIDED += periph_rtc | ||
FEATURES_PROVIDED += periph_spi | ||
FEATURES_PROVIDED += periph_timer | ||
FEATURES_PROVIDED += periph_uart | ||
FEATURES_PROVIDED += periph_usbdev | ||
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# load the common Makefile.features for Nucleo boards | ||
include $(RIOTBOARD)/common/nucleo144/Makefile.features |
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#variable needed by cpy2remed PROGRAMMER | ||
#it contains name of ST-Link removable media | ||
DIR_NAME_AT_REMED = "NODE_F439ZI" | ||
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PROGRAMMERS_SUPPORTED += cpy2remed | ||
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# load the common Makefile.include for Nucleo-144 boards | ||
include $(RIOTBOARD)/common/nucleo144/Makefile.include |
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/** | ||
@defgroup boards_nucleo-f439zi STM32 Nucleo-F439ZI | ||
@ingroup boards_common_nucleo144 | ||
@brief Support for the STM32 Nucleo-F439ZI | ||
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## Flashing the device | ||
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### Flashing the Board Using ST-LINK Removable Media | ||
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On-board ST-LINK programmer provides via composite USB device removable media. | ||
Copying the HEX file causes reprogramming of the board. This task | ||
could be performed manually; however, the cpy2remed (copy to removable | ||
media) PROGRAMMER script does this automatically. To program board in | ||
this manner, use the command: | ||
``` | ||
make BOARD=nucleo-f439zi PROGRAMMER=cpy2remed flash | ||
``` | ||
@note This PROGRAMMER requires ST-LINK firmware 2.37.26 or newer. Firmware updates | ||
could be found on [this STM webpage](https://www.st.com/en/development-tools/stsw-link007.html). | ||
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*/ |
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/* | ||
* Copyright (C) 2022 Inria | ||
* | ||
* This file is subject to the terms and conditions of the GNU Lesser | ||
* General Public License v2.1. See the file LICENSE in the top level | ||
* directory for more details. | ||
*/ | ||
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/** | ||
* @ingroup boards_nucleo-f439zi | ||
* @{ | ||
* | ||
* @file | ||
* @name Peripheral MCU configuration for the nucleo-f439zi board | ||
* | ||
* @author Alexandre Abadie <alexandre.abadie@inria.fr> | ||
*/ | ||
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#ifndef PERIPH_CONF_H | ||
#define PERIPH_CONF_H | ||
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/* This board provides an LSE */ | ||
#ifndef CONFIG_BOARD_HAS_LSE | ||
#define CONFIG_BOARD_HAS_LSE 1 | ||
#endif | ||
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/* This board provides an HSE */ | ||
#ifndef CONFIG_BOARD_HAS_HSE | ||
#define CONFIG_BOARD_HAS_HSE 1 | ||
#endif | ||
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#include "periph_cpu.h" | ||
#include "clk_conf.h" | ||
#include "cfg_i2c1_pb8_pb9.h" | ||
#include "cfg_timer_tim5.h" | ||
#include "cfg_usb_otg_fs.h" | ||
#include "mii.h" | ||
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#ifdef __cplusplus | ||
extern "C" { | ||
#endif | ||
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/** | ||
* @name DMA streams configuration | ||
* @{ | ||
*/ | ||
static const dma_conf_t dma_config[] = { | ||
{ .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */ | ||
{ .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */ | ||
{ .stream = 8 }, /* DMA2 Stream 0 - ETH_TX */ | ||
}; | ||
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#define DMA_0_ISR isr_dma2_stream3 | ||
#define DMA_1_ISR isr_dma2_stream2 | ||
#define DMA_2_ISR isr_dma2_stream0 | ||
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#define DMA_NUMOF ARRAY_SIZE(dma_config) | ||
/** @} */ | ||
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/** | ||
* @name UART configuration | ||
* @{ | ||
*/ | ||
static const uart_conf_t uart_config[] = { | ||
{ | ||
.dev = USART3, | ||
.rcc_mask = RCC_APB1ENR_USART3EN, | ||
.rx_pin = GPIO_PIN(PORT_D, 9), | ||
.tx_pin = GPIO_PIN(PORT_D, 8), | ||
.rx_af = GPIO_AF7, | ||
.tx_af = GPIO_AF7, | ||
.bus = APB1, | ||
.irqn = USART3_IRQn, | ||
#ifdef MODULE_PERIPH_DMA | ||
.dma = DMA_STREAM_UNDEF, | ||
.dma_chan = UINT8_MAX, | ||
#endif | ||
}, | ||
{ | ||
.dev = USART6, | ||
.rcc_mask = RCC_APB2ENR_USART6EN, | ||
.rx_pin = GPIO_PIN(PORT_G, 9), | ||
.tx_pin = GPIO_PIN(PORT_G, 14), | ||
.rx_af = GPIO_AF8, | ||
.tx_af = GPIO_AF8, | ||
.bus = APB2, | ||
.irqn = USART6_IRQn, | ||
#ifdef MODULE_PERIPH_DMA | ||
.dma = DMA_STREAM_UNDEF, | ||
.dma_chan = UINT8_MAX, | ||
#endif | ||
}, | ||
{ | ||
.dev = USART2, | ||
.rcc_mask = RCC_APB1ENR_USART2EN, | ||
.rx_pin = GPIO_PIN(PORT_D, 6), | ||
.tx_pin = GPIO_PIN(PORT_D, 5), | ||
.rx_af = GPIO_AF7, | ||
.tx_af = GPIO_AF7, | ||
.bus = APB1, | ||
.irqn = USART2_IRQn, | ||
#ifdef MODULE_PERIPH_DMA | ||
.dma = DMA_STREAM_UNDEF, | ||
.dma_chan = UINT8_MAX, | ||
#endif | ||
}, | ||
}; | ||
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#define UART_0_ISR (isr_usart3) | ||
#define UART_1_ISR (isr_usart6) | ||
#define UART_2_ISR (isr_usart2) | ||
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#define UART_NUMOF ARRAY_SIZE(uart_config) | ||
/** @} */ | ||
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/** | ||
* @name PWM configuration | ||
* @{ | ||
*/ | ||
static const pwm_conf_t pwm_config[] = { | ||
{ | ||
.dev = TIM1, | ||
.rcc_mask = RCC_APB2ENR_TIM1EN, | ||
.chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0}, | ||
{ .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1}, | ||
{ .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2}, | ||
{ .pin = GPIO_UNDEF, .cc_chan = 0} }, | ||
.af = GPIO_AF1, | ||
.bus = APB2 | ||
}, | ||
{ | ||
.dev = TIM4, | ||
.rcc_mask = RCC_APB1ENR_TIM4EN, | ||
.chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3}, | ||
{ .pin = GPIO_UNDEF, .cc_chan = 0}, | ||
{ .pin = GPIO_UNDEF, .cc_chan = 0}, | ||
{ .pin = GPIO_UNDEF, .cc_chan = 0} }, | ||
.af = GPIO_AF2, | ||
.bus = APB1 | ||
}, | ||
}; | ||
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#define PWM_NUMOF ARRAY_SIZE(pwm_config) | ||
/** @} */ | ||
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/** | ||
* @name SPI configuration | ||
* @{ | ||
*/ | ||
static const spi_conf_t spi_config[] = { | ||
{ | ||
.dev = SPI1, | ||
.mosi_pin = GPIO_PIN(PORT_A, 7), | ||
.miso_pin = GPIO_PIN(PORT_A, 6), | ||
.sclk_pin = GPIO_PIN(PORT_A, 5), | ||
.cs_pin = GPIO_UNDEF, | ||
.mosi_af = GPIO_AF5, | ||
.miso_af = GPIO_AF5, | ||
.sclk_af = GPIO_AF5, | ||
.cs_af = GPIO_AF5, | ||
.rccmask = RCC_APB2ENR_SPI1EN, | ||
.apbbus = APB2, | ||
#ifdef MODULE_PERIPH_DMA | ||
.tx_dma = 0, | ||
.tx_dma_chan = 3, | ||
.rx_dma = 1, | ||
.rx_dma_chan = 3, | ||
#endif | ||
} | ||
}; | ||
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#define SPI_NUMOF ARRAY_SIZE(spi_config) | ||
/** @} */ | ||
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/** | ||
* @name ETH configuration | ||
* @{ | ||
*/ | ||
static const eth_conf_t eth_config = { | ||
.mode = RMII, | ||
.speed = MII_BMCR_SPEED_100 | MII_BMCR_FULL_DPLX, | ||
.dma = 2, | ||
.dma_chan = 8, | ||
.phy_addr = 0x00, | ||
.pins = { | ||
GPIO_PIN(PORT_G, 13), | ||
GPIO_PIN(PORT_B, 13), | ||
GPIO_PIN(PORT_G, 11), | ||
GPIO_PIN(PORT_C, 4), | ||
GPIO_PIN(PORT_C, 5), | ||
GPIO_PIN(PORT_A, 7), | ||
GPIO_PIN(PORT_C, 1), | ||
GPIO_PIN(PORT_A, 2), | ||
GPIO_PIN(PORT_A, 1), | ||
} | ||
}; | ||
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#define ETH_DMA_ISR isr_dma2_stream0 | ||
/** @} */ | ||
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#ifdef __cplusplus | ||
} | ||
#endif | ||
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#endif /* PERIPH_CONF_H */ | ||
/** @} */ |
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