cpu/atmega*: changes for new GPIO API

cpu/atmega1281/include/periph_cpu.h

@@ -40,6 +40,7 @@ enum {
     PORT_E = 4,       /**< port E */
     PORT_F = 5,       /**< port F */
     PORT_G = 6,       /**< port G */
+    GPIO_EXP_PORT = 7 /**< first GPIO expander port */
 };
 
 /**

cpu/atmega1284p/include/periph_cpu.h

@@ -29,19 +29,15 @@
 extern "C" {
 #endif
 
-/**
- * @brief   Define a CPU specific GPIO pin generator macro
- */
-#define GPIO_PIN(x, y)          ((x << 4) | y)
-
 /**
  * @brief   Available ports on the ATmega1284p family
  */
 enum {
     PORT_A = 0,       /**< port A */
     PORT_B = 1,       /**< port B */
     PORT_C = 2,       /**< port C */
-    PORT_D = 3        /**< port D */
+    PORT_D = 3,       /**< port D */
+    GPIO_EXP_PORT = 4 /**< first GPIO expander port */
 };
 
 /**

cpu/atmega128rfa1/include/periph_cpu.h

@@ -32,11 +32,12 @@ extern "C" {
  * @{
  */
 enum {
-    PORT_B  = 1,        /**< port B */
-    PORT_D  = 3,        /**< port D */
-    PORT_E  = 4,        /**< port E */
-    PORT_F  = 5,        /**< port F */
-    PORT_G  = 6,        /**< port G */
+    PORT_B = 1,         /**< port B */
+    PORT_D = 3,         /**< port D */
+    PORT_E = 4,         /**< port E */
+    PORT_F = 5,         /**< port F */
+    PORT_G = 6,         /**< port G */
+    GPIO_EXP_PORT = 7   /**< first GPIO expander port */
 };
 /** @} */
 

cpu/atmega2560/include/periph_cpu.h

@@ -31,17 +31,18 @@ extern "C" {
  * @brief   Available ports on the ATmega2560 family
  */
 enum {
-    PORT_A = 0,       /**< port A */
-    PORT_B = 1,       /**< port B */
-    PORT_C = 2,       /**< port C */
-    PORT_D = 3,       /**< port D */
-    PORT_E = 4,       /**< port E */
-    PORT_F = 5,       /**< port F */
-    PORT_G = 6,       /**< port G */
-    PORT_H = 7,       /**< port H */
-    PORT_J = 8,       /**< port J */
-    PORT_K = 9,       /**< port K */
-    PORT_L = 10       /**< port L */
+    PORT_A = 0,         /**< port A */
+    PORT_B = 1,         /**< port B */
+    PORT_C = 2,         /**< port C */
+    PORT_D = 3,         /**< port D */
+    PORT_E = 4,         /**< port E */
+    PORT_F = 5,         /**< port F */
+    PORT_G = 6,         /**< port G */
+    PORT_H = 7,         /**< port H */
+    PORT_J = 8,         /**< port J */
+    PORT_K = 9,         /**< port K */
+    PORT_L = 10,        /**< port L */
+    GPIO_EXP_PORT = 11  /**< first GPIO expander port */
 };
 
 /**

cpu/atmega256rfr2/include/periph_cpu.h

@@ -32,11 +32,12 @@ extern "C" {
  * @{
  */
 enum {
-    PORT_B  = 1,        /**< port B */
-    PORT_D  = 3,        /**< port D */
-    PORT_E  = 4,        /**< port E */
-    PORT_F  = 5,        /**< port F */
-    PORT_G  = 6,        /**< port G */
+    PORT_B = 1,         /**< port B */
+    PORT_D = 3,         /**< port D */
+    PORT_E = 4,         /**< port E */
+    PORT_F = 5,         /**< port F */
+    PORT_G = 6,         /**< port G */
+    GPIO_EXP_PORT = 7   /**< first GPIO expander port */
 };
 /** @} */
 

cpu/atmega328p/include/periph_cpu.h

@@ -27,18 +27,14 @@
 extern "C" {
 #endif
 
-/**
- * @brief   Define a CPU specific GPIO pin generator macro
- */
-#define GPIO_PIN(x, y)          ((x << 4) | y)
-
 /**
  * @brief   Available ports on the ATmega328p family
  */
 enum {
     PORT_B = 1,       /**< port B */
     PORT_C = 2,       /**< port C */
-    PORT_D = 3        /**< port D */
+    PORT_D = 3,       /**< port D */
+    GPIO_EXP_PORT = 4 /**< first GPIO expander port */
 };
 
 /**

cpu/atmega32u4/include/periph_cpu.h

@@ -34,7 +34,8 @@ enum {
     PORT_C = 2,       /**< port C */
     PORT_D = 3,       /**< port D */
     PORT_E = 4,       /**< port E */
-    PORT_F = 5        /**< port F */
+    PORT_F = 5,       /**< port F */
+    GPIO_EXP_PORT = 6 /**< first GPIO expander port */
 };
 
 /**

cpu/atmega_common/Kconfig

@@ -20,6 +20,7 @@ config CPU_COMMON_ATMEGA
     select HAS_PERIPH_CPUID
     select HAS_PERIPH_EEPROM
     select HAS_PERIPH_GPIO
+    select HAS_PERIPH_GPIO_EXP
     select HAS_PERIPH_GPIO_IRQ
     select HAS_PERIPH_PM
     select HAS_PERIPH_TIMER_PERIODIC

cpu/atmega_common/Makefile.dep

@@ -7,6 +7,9 @@ USEMODULE += atmega_common
 # peripheral drivers are linked into the final binary
 USEMODULE += atmega_common_periph
 
+# 8 bit GPIO pin mask required
+USEMODULE += gpio_mask_8bit
+
 # the atmel port uses stdio_uart
 USEMODULE += stdio_uart
 

cpu/atmega_common/Makefile.features

@@ -3,7 +3,7 @@ FEATURES_PROVIDED += arch_avr8
 FEATURES_PROVIDED += atmega_pcint0
 FEATURES_PROVIDED += periph_cpuid
 FEATURES_PROVIDED += periph_eeprom
-FEATURES_PROVIDED += periph_gpio periph_gpio_irq
+FEATURES_PROVIDED += periph_gpio periph_gpio_irq periph_gpio_exp
 FEATURES_PROVIDED += periph_pm
 FEATURES_PROVIDED += periph_timer_periodic
 FEATURES_PROVIDED += periph_wdt

cpu/atmega_common/include/atmega_gpio.h

@@ -43,55 +43,55 @@ extern "C" {
 #define ATMEGA_GPIO_OFFSET_PIN_PORT (0x02)
 #define ATMEGA_GPIO_OFFSET_PIN_PIN  (0x03)
 
+
 /**
  * @brief     Extract the pin number of the given pin
  */
-static inline uint8_t atmega_pin_num(gpio_t pin)
+static inline uint8_t atmega_pin_num(gpio_pin_t pin)
 {
-    return (pin & 0x0f);
+    return (pin & 0x07);
 }
 
 /**
- * @brief     Extract the port number of the given pin
+ * @brief     Generate the PORTx address of the give port.
  */
-static inline uint8_t atmega_port_num(gpio_t pin)
+static inline gpio_reg_t atmega_port_addr(gpio_port_t port)
 {
-    return (pin >> 4) & 0x0f;
+    return port.reg;
 }
 
 /**
- * @brief     Generate the PORTx address of the give pin.
+ * @brief     Generate the DDRx address of the given port.
  */
-static inline uint16_t atmega_port_addr(gpio_t pin)
+static inline gpio_reg_t atmega_ddr_addr(gpio_port_t port)
 {
-    uint8_t port_num = atmega_port_num(pin);
-    uint16_t port_addr = port_num * ATMEGA_GPIO_OFFSET_PIN_PIN;
-
-    port_addr += ATMEGA_GPIO_BASE_PORT_A;
-    port_addr += ATMEGA_GPIO_OFFSET_PIN_PORT;
-
-#if defined (PORTG)
-    if (port_num > PORT_G) {
-        port_addr += ATMEGA_GPIO_OFFSET_PORT_H;
-    }
-#endif
-    return port_addr;
+    return (atmega_port_addr(port) - 0x01);
 }
 
 /**
- * @brief     Generate the DDRx address of the given pin
+ * @brief     Generate the PINx address of the given port.
  */
-static inline uint16_t atmega_ddr_addr(gpio_t pin)
+static inline gpio_reg_t atmega_pin_addr(gpio_port_t port)
 {
-    return (atmega_port_addr(pin) - 0x01);
+    return (atmega_port_addr(port) - 0x02);
 }
 
 /**
- * @brief     Generate the PINx address of the given pin.
+ * @brief     Generate the port number of the given port
  */
-static inline uint16_t atmega_pin_addr(gpio_t pin)
+static inline uint8_t atmega_port_num(gpio_port_t port)
 {
-    return (atmega_port_addr(pin) - 0x02);
+    gpio_reg_t port_addr = atmega_port_addr(port);
+
+#ifdef PORTG
+    if (port_addr > ATMEGA_GPIO_OFFSET_PORT_H) {
+        port_addr -= ATMEGA_GPIO_OFFSET_PORT_H;
+    }
+#endif
+    port_addr -= ATMEGA_GPIO_OFFSET_PIN_PORT;
+    port_addr -= ATMEGA_GPIO_BASE_PORT_A;
+
+    return port_addr / ATMEGA_GPIO_OFFSET_PIN_PIN;
 }
 
 #ifdef __cplusplus

cpu/atmega_common/include/gpio_arch.h

@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2015 HAW Hamburg
+ *               2016 Freie Universität Berlin
+ *               2016 INRIA
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup         cpu_atmega_common
+ * @{
+ *
+ * @file
+ * @brief           CPU specific definitions for GPIOs
+ *
+ * @author          René Herthel <rene-herthel@outlook.de>
+ * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author          Francisco Acosta <francisco.acosta@inria.fr>
+ */
+
+#ifndef GPIO_ARCH_H
+#define GPIO_ARCH_H
+
+#include "cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef DOXYGEN
+/**
+ * @brief   Defines for port register addresses
+ * @{
+ */
+#define GPIO_PORT_H          (7)
+#define GPIO_BASE_PORT_A     (0x20)
+#define GPIO_OFFSET_PORT_H   (0xCB)
+#define GPIO_OFFSET_PIN_PORT (0x02)
+#define GPIO_OFFSET_PIN_PIN  (0x03)
+/** @} */
+
+/**
+ * @brief   Define a mask for GPIO port register addresses
+ *
+ * In the AVR architecture, the register addresses are between 0x000 and 0x1ff.
+ * Pointers to data in SRAM start at 0x200.
+ */
+#define GPIO_CPU_PORT_MASK   (0xfe00)
+
+/**
+ * @brief   Base register address for MCU GPIO ports
+ */
+#define GPIO_CPU_PORT_BASE   (0x0000)
+
+/**
+ * @brief   Convert a MCU port number into its register address
+ */
+#ifndef PORTH
+#define GPIO_CPU_PORT(x) \
+        ((gpio_reg_t)((x * GPIO_OFFSET_PIN_PIN) + GPIO_BASE_PORT_A \
+                                                + GPIO_OFFSET_PIN_PORT))
+#else
+#define GPIO_CPU_PORT(x) \
+        ((gpio_reg_t)((x < GPIO_PORT_H) ? ((x * GPIO_OFFSET_PIN_PIN) + \
+                                           GPIO_BASE_PORT_A + \
+                                           GPIO_OFFSET_PIN_PORT) \
+                                        : ((x * GPIO_OFFSET_PIN_PIN) + \
+                                           GPIO_BASE_PORT_A + \
+                                           GPIO_OFFSET_PIN_PORT + \
+                                           GPIO_OFFSET_PORT_H)))
+#endif
+
+/**
+ * @brief   Convert a MCU port register address into its port number
+ */
+#ifndef PORTH
+#define GPIO_CPU_PORT_NUM(x) \
+        ((gpio_pin_t)((x - GPIO_OFFSET_PIN_PORT - GPIO_BASE_PORT_A) / GPIO_OFFSET_PIN_PIN))
+#else
+#define GPIO_CPU_PORT_NUM(x) \
+        ((gpio_pin_t)((x > GPIO_OFFSET_PORT_H) ? ((x - GPIO_OFFSET_PORT_H \
+                                                     - GPIO_OFFSET_PIN_PORT \
+                                                     - GPIO_BASE_PORT_A) / GPIO_OFFSET_PIN_PIN) \
+                                               : ((x - GPIO_OFFSET_PIN_PORT \
+                                                     - GPIO_BASE_PORT_A) / GPIO_OFFSET_PIN_PIN)))
+#endif
+
+/**
+ * @brief   Override register address type for GPIO ports of the MCU
+ *
+ * The size of this type must match the size of a pointer to distinguish
+ * between MCU GPIO register addresses and pointers on GPIO devices.
+ */
+#define HAVE_GPIO_REG_T
+typedef uint16_t gpio_reg_t;
+
+/**
+ * @brief   Override the GPIO flanks
+ *
+ * This device has an additional mode in which the interrupt is triggered
+ * when the pin is low.
+ *
+ * Enumeration order is important, do not modify.
+ * @{
+ */
+#define HAVE_GPIO_FLANK_T
+typedef enum {
+    GPIO_LOW,          /**< emit interrupt when pin low */
+    GPIO_BOTH,         /**< emit interrupt on both flanks */
+    GPIO_FALLING,      /**< emit interrupt on falling flank */
+    GPIO_RISING,       /**< emit interrupt on rising flank */
+} gpio_flank_t;
+/** @} */
+#endif /* ndef DOXYGEN */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GPIO_ARCH_H */
+/** @} */