fixup! cpu/fe310: reorganize files and includes

RIOT-OS · Jan 10, 2020 · 75e9799 · 75e9799
1 parent f9d955a
commit 75e9799
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Showing 2 changed files with 15 additions and 12 deletions.
diff --git a/cpu/fe310/cpu.c b/cpu/fe310/cpu.c
@@ -21,14 +21,17 @@
 #include "periph/init.h"
 #include "periph_conf.h"
 
+#include "vendor/encoding.h"
+#include "vendor/plic_driver.h"
+
 /*
  * Configure the memory mapped flash for faster throughput
  * to minimize interrupt latency on an I-Cache miss and refill
  * from flash.  Alternatively (and faster) the interrupt
  * routine could be put in SRAM.  The linker script supports
  * code in SRAM using the ".hotcode" section.
  * The flash chip on the HiFive1 is the ISSI 25LP128
- * http://www.issi.com/WW/pdf/25LP128.pdf
+ * http://www.issi.com/WW/pdf/IS25LP128.pdf
  * The maximum frequency it can run at is 133MHz in
  * "Fast Read Dual I/O" mode.
  * Note the updated data sheet:
@@ -60,14 +63,14 @@ void flash_init(void)
     SPI0_REG(SPI_REG_SCKDIV) = SCKDIV_SAFE;
 
     /* begin{code-style-ignore} */
-    SPI0_REG(SPI_REG_FFMT) =               /* setup "Fast Read Dual I/O"                             */
+    SPI0_REG(SPI_REG_FFMT) =               /* setup "Fast Read Dual I/O" 1-1-2              */
         SPI_INSN_CMD_EN         |          /* Enable memory-mapped flash                    */
-        SPI_INSN_ADDR_LEN(3)    |          /* 25LP03D read commands have 3 address bytes    */
-        SPI_INSN_PAD_CNT(4)     |          /* 25LP03D Table 6.11 Read Dummy Cycles = 4      */
-        SPI_INSN_CMD_PROTO(SPI_PROTO_S) |  /* 25LP03D Table 8.1 "Instruction                */
+        SPI_INSN_ADDR_LEN(3)    |          /* 25LP128 read commands have 3 address bytes    */
+        SPI_INSN_PAD_CNT(4)     |          /* 25LP128 Table 6.9 Read Dummy Cycles P4,P3=0,0 */
+        SPI_INSN_CMD_PROTO(SPI_PROTO_S) |  /* 25LP128 Table 8.1 "Instruction                */
         SPI_INSN_ADDR_PROTO(SPI_PROTO_D) | /*  Set" shows mode for cmd, addr, and           */
         SPI_INSN_DATA_PROTO(SPI_PROTO_D) | /*  data protocol for given instruction          */
-        SPI_INSN_CMD_CODE(0xBB) |          /* Set the instruction to "Fast Read Dual I/O"   */
+        SPI_INSN_CMD_CODE(0xbb) |          /* Set the instruction to "Fast Read Dual I/O"   */
         SPI_INSN_PAD_CODE(0x00);           /* Dummy cycle sends 0 value bits                */
     /* end{code-style-ignore} */
 
@@ -98,6 +101,12 @@ void cpu_init(void)
     flash_init();
 #endif
 
+    /* Enable FPU if present */
+    if (read_csr(misa) & (1 << ('F' - 'A'))) {
+        write_csr(mstatus, MSTATUS_FS); /* allow FPU instructions without trapping */
+        write_csr(fcsr, 0);             /* initialize rounding mode, undefined at reset */
+    }
+
     /* Initialize IRQs */
     irq_init();
 

diff --git a/cpu/fe310/irq_arch.c b/cpu/fe310/irq_arch.c
@@ -56,12 +56,6 @@ void irq_init(void)
     /* Setup trap handler function */
     write_csr(mtvec, &trap_entry);
 
-    /* Enable FPU if present */
-    if (read_csr(misa) & (1 << ('F' - 'A'))) {
-        write_csr(mstatus, MSTATUS_FS); /* allow FPU instructions without trapping */
-        write_csr(fcsr, 0);             /* initialize rounding mode, undefined at reset */
-    }
-
     /* Clear all interrupt enables */
     write_csr(mie, 0);