boards/stm32f0: use shared default clock configuration

RIOT-OS · Aug 30, 2020 · 48a8d29 · 48a8d29
1 parent 88d7ecb
commit 48a8d29
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Showing 9 changed files with 37 additions and 224 deletions.
diff --git a/boards/nucleo-f030r8/include/periph_conf.h b/boards/nucleo-f030r8/include/periph_conf.h
@@ -21,40 +21,16 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
+/* This board provides an LSE */
+#define CLOCK_LSE           (1)
+
 #include "periph_cpu.h"
+#include "f0/cfg_clock_default.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * @name    Clock settings
- *
- * @note    This is auto-generated from
- *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 48MHz */
- #define CLOCK_CORECLOCK      (48000000U)
- /* 0: no external high speed crystal available
-  * else: actual crystal frequency [in Hz] */
- #define CLOCK_HSE            (8000000U)
- /* 0: no external low speed crystal available,
-  * 1: external crystal available (always 32.768kHz) */
- #define CLOCK_LSE            (1)
- /* peripheral clock setup */
- #define CLOCK_AHB_DIV        RCC_CFGR_HPRE_DIV1
- #define CLOCK_AHB            (CLOCK_CORECLOCK / 1)
- #define CLOCK_APB1_DIV       RCC_CFGR_PPRE_DIV1      /* max 48MHz */
- #define CLOCK_APB1           (CLOCK_CORECLOCK / 1)
- #define CLOCK_APB2           (CLOCK_APB1)
-
- /* PLL factors */
- #define CLOCK_PLL_PREDIV     (1)
- #define CLOCK_PLL_MUL        (6)
- /** @} */
-
 /**
  * @name   Timer configuration
  * @{

diff --git a/boards/nucleo-f031k6/include/periph_conf.h b/boards/nucleo-f031k6/include/periph_conf.h
@@ -20,41 +20,21 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
+/* No HSE available on this board */
+#define CLOCK_HSE            (0U)
+
+/* Adjust PLL factors when PLL is clocked by HSI */
+#define CLOCK_PLL_PREDIV     (2)
+#define CLOCK_PLL_MUL        (12)
+
 #include "periph_cpu.h"
+#include "f0/cfg_clock_default.h"
 #include "cfg_timer_tim2.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * @name    Clock settings
- *
- * @note    This is auto-generated from
- *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 48MHz */
-#define CLOCK_CORECLOCK      (48000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE            (0U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE            (0)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV        RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB            (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV       RCC_CFGR_PPRE_DIV1      /* max 48MHz */
-#define CLOCK_APB1           (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2           (CLOCK_APB1)
-
-/* PLL factors */
-#define CLOCK_PLL_PREDIV     (2)
-#define CLOCK_PLL_MUL        (12)
-/** @} */
-
 /**
  * @name UART configuration
  * @{

diff --git a/boards/nucleo-f042k6/include/periph_conf.h b/boards/nucleo-f042k6/include/periph_conf.h
@@ -19,41 +19,21 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
+/* No HSE available on this board */
+#define CLOCK_HSE            (0U)
+
+/* Adjust PLL factors when PLL is clocked by HSI */
+#define CLOCK_PLL_PREDIV     (2)
+#define CLOCK_PLL_MUL        (12)
+
 #include "periph_cpu.h"
+#include "f0/cfg_clock_default.h"
 #include "cfg_timer_tim2.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * @name    Clock settings
- *
- * @note    This is auto-generated from
- *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 48MHz */
-#define CLOCK_CORECLOCK     (48000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE           (0U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE           (0)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV      RCC_CFGR_PPRE_DIV1      /* max 48MHz */
-#define CLOCK_APB1          (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2          (CLOCK_APB1)
-
-/* PLL factors */
-#define CLOCK_PLL_PREDIV     (2)
-#define CLOCK_PLL_MUL        (12)
-/** @} */
-
 /**
  * @name   UART configuration
  * @{

diff --git a/boards/nucleo-f070rb/include/periph_conf.h b/boards/nucleo-f070rb/include/periph_conf.h
@@ -21,41 +21,17 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
+/* This board provides an LSE */
+#define CLOCK_LSE           (1)
+
 #include "periph_cpu.h"
+#include "f0/cfg_clock_default.h"
 #include "cfg_i2c1_pb8_pb9.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * @name    Clock settings
- *
- * @note    This is auto-generated from
- *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 48MHz */
- #define CLOCK_CORECLOCK      (48000000U)
- /* 0: no external high speed crystal available
-  * else: actual crystal frequency [in Hz] */
- #define CLOCK_HSE            (8000000U)
- /* 0: no external low speed crystal available,
-  * 1: external crystal available (always 32.768kHz) */
- #define CLOCK_LSE            (1)
- /* peripheral clock setup */
- #define CLOCK_AHB_DIV        RCC_CFGR_HPRE_DIV1
- #define CLOCK_AHB            (CLOCK_CORECLOCK / 1)
- #define CLOCK_APB1_DIV       RCC_CFGR_PPRE_DIV1      /* max 48MHz */
- #define CLOCK_APB1           (CLOCK_CORECLOCK / 1)
- #define CLOCK_APB2           (CLOCK_APB1)
-
- /* PLL factors */
- #define CLOCK_PLL_PREDIV     (1)
- #define CLOCK_PLL_MUL        (6)
- /** @} */
-
 /**
  * @name   Timer configuration
  * @{

diff --git a/boards/nucleo-f072rb/include/periph_conf.h b/boards/nucleo-f072rb/include/periph_conf.h
@@ -20,41 +20,17 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
+/* This board provides an LSE */
+#define CLOCK_LSE           (1)
+
 #include "periph_cpu.h"
+#include "f0/cfg_clock_default.h"
 #include "cfg_i2c1_pb8_pb9.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * @name    Clock settings
- *
- * @note    This is auto-generated from
- *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 48MHz */
- #define CLOCK_CORECLOCK      (48000000U)
- /* 0: no external high speed crystal available
-  * else: actual crystal frequency [in Hz] */
- #define CLOCK_HSE            (8000000U)
- /* 0: no external low speed crystal available,
-  * 1: external crystal available (always 32.768kHz) */
- #define CLOCK_LSE            (1)
- /* peripheral clock setup */
- #define CLOCK_AHB_DIV        RCC_CFGR_HPRE_DIV1
- #define CLOCK_AHB            (CLOCK_CORECLOCK / 1)
- #define CLOCK_APB1_DIV       RCC_CFGR_PPRE_DIV1      /* max 48MHz */
- #define CLOCK_APB1           (CLOCK_CORECLOCK / 1)
- #define CLOCK_APB2           (CLOCK_APB1)
-
- /* PLL factors */
- #define CLOCK_PLL_PREDIV     (1)
- #define CLOCK_PLL_MUL        (6)
- /** @} */
-
 /**
  * @name   Timer configuration
  * @{

diff --git a/boards/nucleo-f091rc/include/periph_conf.h b/boards/nucleo-f091rc/include/periph_conf.h
@@ -19,41 +19,17 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
+/* This board provides an LSE */
+#define CLOCK_LSE           (1)
+
 #include "periph_cpu.h"
+#include "f0/cfg_clock_default.h"
 #include "cfg_i2c1_pb8_pb9.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * @name    Clock settings
- *
- * @note    This is auto-generated from
- *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 48MHz */
-#define CLOCK_CORECLOCK      (48000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE            (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE            (1)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV        RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB            (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV       RCC_CFGR_PPRE_DIV1      /* max 48MHz */
-#define CLOCK_APB1           (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2           (CLOCK_APB1)
-
-/* PLL factors */
-#define CLOCK_PLL_PREDIV     (1)
-#define CLOCK_PLL_MUL        (6)
-/** @} */
-
 /**
  * @name    DMA streams configuration
  * @{

diff --git a/boards/stm32f030f4-demo/include/periph_conf.h b/boards/stm32f030f4-demo/include/periph_conf.h
@@ -23,39 +23,12 @@
 #define PERIPH_CONF_H
 
 #include "periph_cpu.h"
+#include "f0/cfg_clock_default.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * @name    Clock settings
- *
- * @note    This is auto-generated from
- *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 48MHz */
- #define CLOCK_CORECLOCK      (48000000U)
- /* 0: no external high speed crystal available
-  * else: actual crystal frequency [in Hz] */
- #define CLOCK_HSE            (8000000U)
- /* 0: no external low speed crystal available,
-  * 1: external crystal available (always 32.768kHz) */
- #define CLOCK_LSE            (0)
- /* peripheral clock setup */
- #define CLOCK_AHB_DIV        RCC_CFGR_HPRE_DIV1
- #define CLOCK_AHB            (CLOCK_CORECLOCK / 1)
- #define CLOCK_APB1_DIV       RCC_CFGR_PPRE_DIV1      /* max 48MHz */
- #define CLOCK_APB1           (CLOCK_CORECLOCK / 1)
- #define CLOCK_APB2           (CLOCK_APB1)
-
- /* PLL factors */
- #define CLOCK_PLL_PREDIV     (1)
- #define CLOCK_PLL_MUL        (6)
- /** @} */
-
 /**
  * @name   Timer configuration
  * @{

diff --git a/boards/stm32f0discovery/Makefile.include b/boards/stm32f0discovery/Makefile.include
@@ -1,3 +1,6 @@
+# we use shared STM32 configuration snippets
+INCLUDES += -I$(RIOTBASE)/boards/common/stm32/include
+
 # define the default port depending on the host OS
 PORT_LINUX ?= /dev/ttyUSB0
 PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))

diff --git a/boards/stm32f0discovery/include/periph_conf.h b/boards/stm32f0discovery/include/periph_conf.h
@@ -20,39 +20,12 @@
 #define PERIPH_CONF_H
 
 #include "periph_cpu.h"
+#include "f0/cfg_clock_default.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * @name    Clock settings
- *
- * @note    This is auto-generated from
- *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 48MHz */
-#define CLOCK_CORECLOCK      (48000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE            (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE            (0)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV        RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB            (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV       RCC_CFGR_PPRE_DIV1      /* max 48MHz */
-#define CLOCK_APB1           (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2           (CLOCK_APB1)
-
-/* PLL factors */
-#define CLOCK_PLL_PREDIV     (1)
-#define CLOCK_PLL_MUL        (6)
-/** @} */
-
 /**
  * @name   Timer configuration
  * @{