Merge pull request #19736 from firas-hamdi/cpu/samd5x-write-CAN-driver

cpu/samd5x write can driver

boards/same54-xpro/Makefile.features

@@ -16,6 +16,7 @@ FEATURES_PROVIDED += periph_uart_hw_fc
 FEATURES_PROVIDED += periph_adc
 FEATURES_PROVIDED += periph_usbdev
 FEATURES_PROVIDED += periph_freqm
+FEATURES_PROVIDED += periph_can
 
 # Put other features for this board (in alphabetical order)
 FEATURES_PROVIDED += riotboot

boards/same54-xpro/include/board.h

@@ -75,6 +75,13 @@ extern "C" {
 #define BTN0_MODE           GPIO_IN_PU
 /** @} */
 
+/**
+ * @name ATA6561 STANDBY pin definition
+ * @{
+ */
+#define AT6561_STBY_PIN            GPIO_PIN(PC, 13)
+/** @} */
+
 /**
  * @name MTD configuration
  * @{

boards/same54-xpro/include/periph_conf.h

@@ -106,6 +106,27 @@ static const tc32_conf_t timer_config[] = {
 #define TIMER_NUMOF         ARRAY_SIZE(timer_config)
 /** @} */
 
+/**
+ * @name CAN configuration
+ * @{
+ */
+/** Available CAN interfaces */
+static const can_conf_t candev_conf[] = {
+    {
+        .can = CAN1,
+        .rx_pin = GPIO_PIN(PB, 13),
+        .tx_pin = GPIO_PIN(PB, 12),
+        .gclk_src = SAM0_GCLK_PERIPH,
+    }
+};
+
+/** CAN 1 configuration */
+#define ISR_CAN1    isr_can1
+
+/** Number of CAN interfaces */
+#define CAN_NUMOF         ARRAY_SIZE(candev_conf)
+/** @} */
+
 /**
  * @name UART configuration
  * @{

cpu/samd5x/Makefile.dep

@@ -2,4 +2,8 @@ ifneq (,$(filter periph_gpio_tamper_wake,$(USEMODULE)))
   USEMODULE += periph_rtc_rtt
 endif
 
+ifneq (,$(filter periph_can,$(USEMODULE)))
+  FEATURES_REQUIRED += can_rx_mailbox
+endif
+
 include $(RIOTCPU)/sam0_common/Makefile.dep

cpu/samd5x/Makefile.features

@@ -7,5 +7,6 @@ FEATURES_PROVIDED += periph_gpio_tamper_wake
 FEATURES_PROVIDED += periph_rtc_mem
 FEATURES_PROVIDED += periph_spi_on_qspi
 FEATURES_PROVIDED += periph_uart_collision
+FEATURES_PROVIDED += can_rx_mailbox
 
 include $(RIOTCPU)/sam0_common/Makefile.features

cpu/samd5x/include/can_params.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2024 ML!PA Consulting GmbH
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup         cpu_samd5x
+ * @brief           CPU specific definitions for CAN controllers
+ * @{
+ *
+ * @file
+ * @brief           SAMD5x CAN controller (M_CAN Bosch) default device parameters
+ *
+ * @author          Firas Hamdi <firas.hamdi@ml-pa.com>
+ */
+
+#ifndef CAN_PARAMS_H
+#define CAN_PARAMS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "can/device.h"
+
+/** Default SAMD5x CAN devices parameters */
+static const candev_params_t candev_params[] = {
+    {
+        .name = "can_samd5x_0",
+    },
+    {
+        .name = "can_samd5x_1",
+    }
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CAN_PARAMS_H */
+/** @} */

cpu/samd5x/include/candev_samd5x.h

@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2024 ML!PA Consulting GmbH
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup         cpu_samd5x
+ * @brief           CPU specific definitions for CAN controllers
+ * @{
+ *
+ * @file
+ * @brief           SAMD5x CAN controller (M_CAN Bosch) driver
+ *
+ * @author          Firas Hamdi <firas.hamdi@ml-pa.com>
+ */
+
+#ifndef CANDEV_SAMD5X_H
+#define CANDEV_SAMD5X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(CAN_INST_NUM)
+#include "can/candev.h"
+
+#ifndef CANDEV_SAMD5X_DEFAULT_BITRATE
+/** Default bitrate */
+#define CANDEV_SAMD5X_DEFAULT_BITRATE 500000U
+#endif
+
+#ifndef CANDEV_SAMD5X_DEFAULT_SPT
+/** Default sampling-point */
+#define CANDEV_SAMD5X_DEFAULT_SPT 875
+#endif
+
+#ifndef CANDEV_SAMD5X_DEFAULT_STD_FILTER_NUM
+#define CANDEV_SAMD5X_DEFAULT_STD_FILTER_NUM 3
+#endif
+
+#ifndef CANDEV_SAMD5X_DEFAULT_EXT_FILTER_NUM
+#define CANDEV_SAMD5X_DEFAULT_EXT_FILTER_NUM 3
+#endif
+
+#ifndef CANDEV_SAMD5X_DEFAULT_RX_FIFO_0_ELTS_NUM
+#define CANDEV_SAMD5X_DEFAULT_RX_FIFO_0_ELTS_NUM 32
+#endif
+
+#ifndef CANDEV_SAMD5X_DEFAULT_RX_FIFO_1_ELTS_NUM
+#define CANDEV_SAMD5X_DEFAULT_RX_FIFO_1_ELTS_NUM 32
+#endif
+
+#ifndef CANDEV_SAMD5X_DEFAULT_TX_EVT_FIFO_ELTS_NUM
+#define CANDEV_SAMD5X_DEFAULT_TX_EVT_FIFO_ELTS_NUM 16
+#endif
+
+#ifndef CANDEV_SAMD5X_DEFAULT_TX_BUFFER_NUM
+#define CANDEV_SAMD5X_DEFAULT_TX_BUFFER_NUM 16
+#endif
+
+#ifndef CANDEV_SAMD5X_DEFAULT_TX_BUFFER_FIFO_QUEUE_NUM
+#define CANDEV_SAMD5X_DEFAULT_TX_BUFFER_FIFO_QUEUE_NUM 16
+#endif
+
+/* unit: elements */
+#define CANDEV_SAMD5X_MAX_STD_FILTER 128
+#define CANDEV_SAMD5X_MAX_EXT_FILTER 64
+#define CANDEV_SAMD5X_MAX_RX_FIFO_0_ELTS 64
+#define CANDEV_SAMD5X_MAX_RX_FIFO_1_ELTS 64
+#define CANDEV_SAMD5X_MAX_RX_BUFFER 64
+#define CANDEV_SAMD5X_MAX_TX_EVT_FIFO_ELTS 32
+#define CANDEV_SAMD5X_MAX_TX_BUFFER 32
+#define CANDEV_SAMD5X_MSG_RAM_MAX_SIZE 448
+
+/**
+ * @brief CAN device configuration descriptor
+ */
+typedef struct {
+    /** CAN device handler */
+    Can *can;
+    /** CAN Rx pin */
+    gpio_t rx_pin;
+    /** CAN Tx pin */
+    gpio_t tx_pin;
+    /** GCLK source supplying the CAN controller */
+    uint8_t gclk_src;
+} can_conf_t;
+#define HAVE_CAN_CONF_T
+
+/**
+ * @brief CAN message RAM accessible to the CAN controller
+ */
+typedef struct {
+    /** Standard filters space in the CAN message RAM */
+    CanMramSidfe std_filter[CANDEV_SAMD5X_DEFAULT_STD_FILTER_NUM];
+    /** Extended filters space in the CAN message RAM */
+    CanMramXifde ext_filter[CANDEV_SAMD5X_DEFAULT_EXT_FILTER_NUM];
+    /** Reception FIFO_0 space in the CAN message RAM */
+    CanMramRxf0e rx_fifo_0[CANDEV_SAMD5X_DEFAULT_RX_FIFO_0_ELTS_NUM];
+    /** Reception FIFO_1 space in the CAN message RAM */
+    CanMramRxf1e rx_fifo_1[CANDEV_SAMD5X_DEFAULT_RX_FIFO_1_ELTS_NUM];
+    /** Reception buffers space in the CAN message RAM */
+    CanMramRxbe rx_buffer[CANDEV_SAMD5X_MAX_RX_BUFFER];
+    /** Transmission events FIFO space in the CAN message RAM */
+    CanMramTxefe tx_event_fifo[CANDEV_SAMD5X_DEFAULT_TX_EVT_FIFO_ELTS_NUM];
+    /** Transmission FIFO space in the CAN message RAM */
+    CanMramTxbe tx_fifo_queue[CANDEV_SAMD5X_DEFAULT_TX_BUFFER_FIFO_QUEUE_NUM];
+} msg_ram_conf_t;
+
+/**
+ * @brief CAN device descriptor
+ */
+typedef struct {
+    /** Structure to hold driver state */
+    candev_t candev;
+    /** CAN device configuration descriptor */
+    const can_conf_t *conf;
+    /** CAN message RAM accessible to the CAN controller */
+    msg_ram_conf_t msg_ram_conf;
+    /** Enable/Disable Transceiver Delay Compensation */
+    bool tdc_ctrl;
+    /** False to use Tx FIFO operation, True to use Tx Queue operation */
+    bool tx_fifo_queue_ctrl;
+} can_t;
+#define HAVE_CAN_T
+
+/**
+ * @brief   Enable/Disable the transmitter delay compensation
+ *
+ * @param[in] dev   device descriptor
+ *
+ */
+void candev_samd5x_tdc_control(can_t *dev);
+
+/**
+ * @brief   Enter the device into sleep mode
+ *
+ * @param[in] candev   candev driver
+ *
+ */
+void candev_samd5x_enter_sleep_mode(candev_t *candev);
+
+/**
+ * @brief   Wake up the device from sleep mode
+ *
+ * @param[in] candev   candev driver
+ *
+ */
+void candev_samd5x_exit_sleep_mode(candev_t *candev);
+
+#endif /* CAN_INST_NUM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CANDEV_SAMD5X_H */
+/** @} */

cpu/samd5x/include/periph_cpu.h

@@ -25,6 +25,7 @@
 #include "macros/units.h"
 #include "periph_cpu_common.h"
 
+#include "candev_samd5x.h"
 #ifdef __cplusplus
 extern "C" {
 #endif