Merge branch 'develop'

README.md

@@ -83,7 +83,7 @@ Requirements
 --------------------
 
 - Python: 3.7.7 or later
-    - Python 3.9.5 (via pyenv) is recommended for macOS with Apple Silicon.
+    - Python 3.9.5 or later version is recommended for macOS with Apple Silicon.
 - Icarus Verilog: 10.1 or later
 
 ```

examples/axi_stream_ultra96v2_pynq/test_axi_stream.py

@@ -189,7 +189,7 @@
                                 (axis_maskaddr_13 == 1)? _saxi_resetval_1 : 
                                 (axis_maskaddr_13 == 2)? _saxi_resetval_2 : 
                                 (axis_maskaddr_13 == 3)? _saxi_resetval_3 : 'hx;
-  reg _saxi_cond_0_1;
+  reg _saxi_rdata_cond_0_1;
   assign saxi_wready = _saxi_register_fsm == 3;
   reg [32-1:0] th_comp;
   localparam th_comp_init = 0;
@@ -235,7 +235,6 @@
 
   always @(posedge CLK) begin
     if(RST) begin
-      _axi_b_write_data_busy <= 0;
       axi_b_tdata <= 0;
       axi_b_tvalid <= 0;
       axi_b_tlast <= 0;
@@ -245,9 +244,6 @@
         axi_b_tvalid <= 0;
         axi_b_tlast <= 0;
       end 
-      if((th_comp == 12) && _axi_b_write_idle) begin
-        _axi_b_write_data_busy <= 1;
-      end 
       if((th_comp == 13) && (axi_b_tready || !axi_b_tvalid)) begin
         axi_b_tdata <= _th_comp_b_4;
         axi_b_tvalid <= 1;
@@ -258,6 +254,17 @@
         axi_b_tvalid <= axi_b_tvalid;
         axi_b_tlast <= axi_b_tlast;
       end 
+    end
+  end
+
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      _axi_b_write_data_busy <= 0;
+    end else begin
+      if((th_comp == 12) && _axi_b_write_idle) begin
+        _axi_b_write_data_busy <= 1;
+      end 
       if((th_comp == 13) && (axi_b_tready || !axi_b_tvalid)) begin
         _axi_b_write_data_busy <= 0;
       end 
@@ -280,6 +287,27 @@
   end
 
 
+  always @(posedge CLK) begin
+    if(RST) begin
+      saxi_rdata <= 0;
+      saxi_rvalid <= 0;
+      _saxi_rdata_cond_0_1 <= 0;
+    end else begin
+      if(_saxi_rdata_cond_0_1) begin
+        saxi_rvalid <= 0;
+      end 
+      if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin
+        saxi_rdata <= axislite_rdata_14;
+        saxi_rvalid <= 1;
+      end 
+      _saxi_rdata_cond_0_1 <= 1;
+      if(saxi_rvalid && !saxi_rready) begin
+        saxi_rvalid <= saxi_rvalid;
+      end 
+    end
+  end
+
+
   always @(posedge CLK) begin
     if(RST) begin
       saxi_bvalid <= 0;
@@ -288,9 +316,6 @@
       writevalid_9 <= 0;
       readvalid_10 <= 0;
       addr_8 <= 0;
-      saxi_rdata <= 0;
-      saxi_rvalid <= 0;
-      _saxi_cond_0_1 <= 0;
       _saxi_register_0 <= 0;
       _saxi_flag_0 <= 0;
       _saxi_register_1 <= 0;
@@ -300,9 +325,6 @@
       _saxi_register_3 <= 0;
       _saxi_flag_3 <= 0;
     end else begin
-      if(_saxi_cond_0_1) begin
-        saxi_rvalid <= 0;
-      end 
       if(saxi_bvalid && saxi_bready) begin
         saxi_bvalid <= 0;
       end 
@@ -320,14 +342,6 @@
         addr_8 <= saxi_araddr;
         readvalid_10 <= 1;
       end 
-      if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin
-        saxi_rdata <= axislite_rdata_14;
-        saxi_rvalid <= 1;
-      end 
-      _saxi_cond_0_1 <= 1;
-      if(saxi_rvalid && !saxi_rready) begin
-        saxi_rvalid <= saxi_rvalid;
-      end 
       if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_15 && (axis_maskaddr_13 == 0)) begin
         _saxi_register_0 <= axislite_resetval_16;
         _saxi_flag_0 <= 0;

examples/axi_stream_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py

@@ -81,4 +81,3 @@
 
 diff_sum = np.sum(expected - dst)
 print(diff_sum)
-

examples/chatter_clear/test_chatter_clear.py

@@ -185,6 +185,7 @@
 endmodule
 """
 
+
 def test():
     veriloggen.reset()
     test_module = chatter_clear.mkTest()

examples/counter/test_counter.py

@@ -90,6 +90,7 @@
 endmodule
 """
 
+
 def test():
     veriloggen.reset()
     test_module = counter.mkTest()

examples/led/test_led.py

@@ -82,6 +82,7 @@
 endmodule
 """
 
+
 def test():
     veriloggen.reset()
     test_module = led.mkTest()

examples/manyled/manyled.py

@@ -8,6 +8,7 @@
 
 from veriloggen import *
 
+
 def mkLed():
     m = Module('blinkled')
     width = m.Parameter('WIDTH', 8)
@@ -16,8 +17,8 @@ def mkLed():
 
     # function to add an LED port
     def add_led(postfix, limit=1024):
-        led = m.OutputReg('LED'+postfix, width)
-        count = m.Reg('count'+postfix, 32)
+        led = m.OutputReg('LED' + postfix, width)
+        count = m.Reg('count' + postfix, 32)
 
         m.Always(Posedge(clk))(
             If(rst)(
@@ -29,7 +30,7 @@ def add_led(postfix, limit=1024):
                     count(count + 1)
                 )
             ))
-    
+
         m.Always(Posedge(clk))(
             If(rst)(
                 led(0)
@@ -41,10 +42,11 @@ def add_led(postfix, limit=1024):
 
     # call 'add_led' to add LED ports
     for i in range(4):
-        add_led('_' + str(i), limit=i*10 + 10)
-    
+        add_led('_' + str(i), limit=i * 10 + 10)
+
     return m
 
+
 if __name__ == '__main__':
     led = mkLed()
     verilog = led.to_verilog()

examples/manyled/test_manyled.py

@@ -103,6 +103,7 @@
 endmodule
 """
 
+
 def test():
     veriloggen.reset()
     test_module = manyled.mkLed()

examples/read_verilog_code/read_verilog_code.py

@@ -43,23 +43,25 @@
 endmodule
 '''
 
+
 def mkLed():
     modules = from_verilog.read_verilog_module_str(led_v)
     m = modules['blinkled']
-    
+
     # change the module name
     m.name = 'modified_led'
-    
+
     # add new statements
     enable = m.Input('enable')
     busy = m.Output('busy')
 
     old_statement = m.always[0].statement[0].false_statement
     m.always[0].statement[0].false_statement = If(enable)(*old_statement)
-    m.Assign( busy(m.variable['count'] < 1023) )
-    
+    m.Assign(busy(m.variable['count'] < 1023))
+
     return m
 
+
 if __name__ == '__main__':
     led = mkLed()
     verilog = led.to_verilog()

examples/read_verilog_code/test_read_verilog_code.py

@@ -40,6 +40,7 @@
 endmodule
 """
 
+
 def test():
     veriloggen.reset()
     test_module = read_verilog_code.mkLed()