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  • Accenture
  • Ottawa

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Pritam-Sethuraman/README.md

Cover Image

Hi there πŸ‘‹

πŸ’« About Me:

πŸŽ“ Master's in Electrical and Computer Engineering from Concordia University
🌱 My key interests are in ASIC Design and Verification
πŸ’» I'm proficient in VHDL, Verilog, SystemVerilog and UVM
πŸ‘― I’m looking to collaborate on projects related to ASIC design and verification
πŸ’¬ Ask me about anything related to ASIC Design and Verification

🌐 Socials:

LinkedIn Email

πŸ’» Tech Stack:

Python JavaScript VHDL SystemVerilog UVM Arduino Raspberry Pi Notion


visitors

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