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GSoC project: Enhancing OpenPiton+Ariane With a High-Performance Data Cache #136

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55296d1
Added ariane+HPDC repository
AileonN Jun 19, 2023
81d9730
Support for building the HPDC files
AileonN Jun 19, 2023
7199cbe
Update ariane submodule commit
AileonN Jul 20, 2023
0e4fd2f
Update ariane submodule commit
AileonN Jul 21, 2023
a09008f
Invalidation first draft
AileonN Jul 31, 2023
26de10b
Fix: Store requests must send the data replicated
AileonN Aug 1, 2023
f4addc6
Fix: Invalidations asserts
AileonN Aug 7, 2023
5295086
Fix: Uncached L1.5 responses
AileonN Aug 7, 2023
7a1a73d
Added support for AMOs
AileonN Aug 10, 2023
85afabc
Bug fix: Inval address when L1.5 evicts and Back-off for lrsc added
AileonN Aug 22, 2023
9bffd6b
Bug fix: Onehot access to cache directory (invals and amo)
AileonN Aug 23, 2023
94f1656
Bug fixed: WBUF coalescing
AileonN Aug 30, 2023
cd60837
Write coalescing enabled (WRITE_BYTE_MASK)
AileonN Sep 7, 2023
5e08dd0
Bug fix: PITON_NO_CHIP_BRIDGE
AileonN Sep 12, 2023
892f8b4
ft added: Free thid list
AileonN Sep 14, 2023
921cbb2
Enabled the possibility to use or not WRITE_BYTE_MASK
AileonN Sep 19, 2023
db65fb1
Added some comments & parametric thid free list
AileonN Sep 21, 2023
688758f
ft added: Parametric size of I$ non cachable requests
AileonN Oct 27, 2023
3ae2c16
INVAL fifo entries increased to a high value.
AileonN Oct 27, 2023
2647945
Changing inval address signal + Added PITON_ARIANE_HPDC macro
AileonN Oct 28, 2023
74385c0
Solved compile errors due to monitor and flist
AileonN Oct 28, 2023
a783e99
Added parametric PID
AileonN Nov 17, 2023
8dc5ba5
ft: Supporting HPDC VIPT version
AileonN Feb 5, 2024
1b97ffa
Updating to last version of HPDC (CMO incompatibilities solved)
AileonN Feb 12, 2024
c3428c7
Fix: WBUF fifo feedthrough disabled
AileonN Feb 13, 2024
ac7fc92
HPDC pointer changed to master branch
AileonN Feb 13, 2024
be03e01
ft: Shared interface for invals and refills
AileonN Feb 22, 2024
06ff90f
fix: Icache inval address
AileonN Feb 26, 2024
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6 changes: 3 additions & 3 deletions .gitmodules
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
[submodule "piton/design/chip/tile/ariane"]
path = piton/design/chip/tile/ariane
url = https://github.com/pulp-platform/ariane.git
[submodule "aws"]
path = piton/design/aws
url = https://github.com/PrincetonUniversity/openpiton-aws.git
[submodule "piton/design/chipset/rv64_platform/bootrom/u-boot/uboot"]
path = piton/design/chipset/rv64_platform/bootrom/u-boot/uboot
url = git@github.com:u-boot/u-boot.git
[submodule "piton/design/chip/tile/ariane"]
path = piton/design/chip/tile/ariane
url = https://github.com/AileonN/cva6_openpiton_noliete.git
2 changes: 1 addition & 1 deletion piton/design/chip/tile/ariane
Open in desktop
Submodule ariane updated 24 files
+3 −0 .gitmodules
+16 −0 Flist.ariane
+1 −0 Flist.hpdc_param
+3 −1 Makefile
+307 −0 core/cache_subsystem/cva6_hpdcache_if_adapter.sv
+347 −0 core/cache_subsystem/cva6_hpdcache_load_if_adapter.sv
+716 −0 core/cache_subsystem/cva6_hpdcache_subsystem.sv
+586 −0 core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv
+484 −0 core/cache_subsystem/cva6_hpdcache_subsystem_l15_adapter.sv
+6 −1 core/cache_subsystem/wt_dcache_ctrl.sv
+6 −5 core/cache_subsystem/wt_l15_adapter.sv
+71 −3 core/cva6.sv
+20 −2 core/include/ariane_pkg.sv
+1 −0 core/include/cv32a60x_config_pkg.sv
+1 −0 core/include/cv32a6_imac_sv0_config_pkg.sv
+1 −0 core/include/cv32a6_imac_sv32_config_pkg.sv
+1 −0 core/include/cv32a6_imafc_sv32_config_pkg.sv
+1 −0 core/include/cv64a6_imafdc_sv39_config_pkg.sv
+3 −0 core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
+8 −3 core/include/wt_cache_pkg.sv
+130 −80 core/load_unit.sv
+8 −2 corev_apu/openpiton/ariane_verilog_wrap.sv
+4 −1 corev_apu/tb/ariane_soc_pkg.sv
+1 −0 cv-hpdcache
21 changes: 16 additions & 5 deletions piton/design/chip/tile/l15/rtl/l15.v
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Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,9 @@ module l15 (
input [63:0] transducer_l15_data,
input [63:0] transducer_l15_data_next_entry,
input [`TLB_CSM_WIDTH-1:0] transducer_l15_csm_data,
`ifdef WRITE_BYTE_MASK
input [`L15_BYTE_MASK_WIDHT-1:0] transducer_l15_be,
`endif

output l15_transducer_ack,
output l15_transducer_header_ack,
Expand All @@ -85,7 +88,7 @@ module l15 (
output [63:0] l15_transducer_data_3,
output l15_transducer_inval_icache_all_way,
output l15_transducer_inval_dcache_all_way,
output [15:4] l15_transducer_inval_address_15_4,
output [`L15_PADDR_MASK] l15_transducer_inval_address,
output l15_transducer_cross_invalidate,
output [1:0] l15_transducer_cross_invalidate_way,
output l15_transducer_inval_dcache_inval,
Expand Down Expand Up @@ -486,6 +489,7 @@ wire [`L15_MSHR_ID_WIDTH-1:0] pipe_mshr_readreq_mshrid_s1;
wire [`L15_CONTROL_WIDTH-1:0] mshr_pipe_readres_control_s1;
wire [`PACKET_HOME_ID_WIDTH-1:0] mshr_pipe_readres_homeid_s1;
wire [(`L15_NUM_MSHRID_PER_THREAD*`L15_NUM_THREADS)-1:0] mshr_pipe_vals_s1;
wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ifill_address;
wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ld_address;
wire [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_st_address;
wire [(2*`L15_NUM_THREADS)-1:0] mshr_pipe_st_way_s1;
Expand Down Expand Up @@ -522,6 +526,7 @@ l15_mshr mshr(
.mshr_pipe_readres_control_s1(mshr_pipe_readres_control_s1),
.mshr_pipe_readres_homeid_s1(mshr_pipe_readres_homeid_s1),
.mshr_pipe_vals_s1(mshr_pipe_vals_s1),
.mshr_pipe_ifill_address(mshr_pipe_ifill_address),
.mshr_pipe_ld_address(mshr_pipe_ld_address),
.mshr_pipe_st_address(mshr_pipe_st_address),
.mshr_pipe_st_way_s1(mshr_pipe_st_way_s1),
Expand Down Expand Up @@ -608,7 +613,7 @@ rf_l15_lrsc_flag lrsc_flag(
// );



`ifndef PITON_ARIANE_HPDC // L1D is NOT HPDC
// way map table
wire l15_wmt_read_val_s2;
wire [`L1D_SET_IDX_MASK] l15_wmt_read_index_s2;
Expand All @@ -628,7 +633,7 @@ rf_l15_wmt wmc(
.write_data(l15_wmt_write_data_s3),
.read_data(wmt_l15_data_s3)
);

`endif
// lru array, psuedo
wire l15_lruarray_read_val_s1;
wire [`L15_CACHE_INDEX_WIDTH-1:0] l15_lruarray_read_index_s1;
Expand Down Expand Up @@ -658,7 +663,6 @@ l15_pipeline pipeline(
.mesi_l15_dout_s2(mesi_l15_dout_s2),
.lrsc_flag_l15_dout_s2(lrsc_flag_l15_dout_s2),
.lruarray_l15_dout_s2(lruarray_l15_dout_s2),
.wmt_l15_data_s3(wmt_l15_data_s3),
.pcxdecoder_l15_rqtype (transducer_l15_rqtype),
.pcxdecoder_l15_amo_op (transducer_l15_amo_op),
.pcxdecoder_l15_nc (transducer_l15_nc),
Expand All @@ -675,6 +679,9 @@ l15_pipeline pipeline(
.pcxdecoder_l15_data (transducer_l15_data),
.pcxdecoder_l15_data_next_entry (transducer_l15_data_next_entry),
.pcxdecoder_l15_csm_data (transducer_l15_csm_data),
`ifdef WRITE_BYTE_MASK
.pcxdecoder_l15_be (transducer_l15_be),
`endif
.noc2decoder_l15_val(noc2decoder_l15_val),
.noc2decoder_l15_mshrid(noc2decoder_l15_mshrid),
.noc2decoder_l15_l2miss(noc2decoder_l15_l2miss),
Expand Down Expand Up @@ -724,12 +731,15 @@ l15_pipeline pipeline(
.l15_lrsc_flag_write_index_s2(l15_lrsc_flag_write_index_s2),
.l15_lrsc_flag_write_mask_s2(l15_lrsc_flag_write_mask_s2),
.l15_lrsc_flag_write_data_s2(l15_lrsc_flag_write_data_s2),
`ifndef PITON_ARIANE_HPDC
.l15_wmt_read_val_s2(l15_wmt_read_val_s2),
.l15_wmt_read_index_s2(l15_wmt_read_index_s2),
.wmt_l15_data_s3(wmt_l15_data_s3),
.l15_wmt_write_val_s3(l15_wmt_write_val_s3),
.l15_wmt_write_index_s3(l15_wmt_write_index_s3),
.l15_wmt_write_mask_s3(l15_wmt_write_mask_s3),
.l15_wmt_write_data_s3(l15_wmt_write_data_s3),
`endif
.l15_lruarray_read_val_s1(l15_lruarray_read_val_s1),
.l15_lruarray_read_index_s1(l15_lruarray_read_index_s1),
.l15_lruarray_write_val_s3(l15_lruarray_write_val_s3),
Expand All @@ -751,7 +761,7 @@ l15_pipeline pipeline(
.l15_cpxencoder_data_3 (l15_transducer_data_3),
.l15_cpxencoder_inval_icache_all_way (l15_transducer_inval_icache_all_way),
.l15_cpxencoder_inval_dcache_all_way (l15_transducer_inval_dcache_all_way),
.l15_cpxencoder_inval_address_15_4 (l15_transducer_inval_address_15_4),
.l15_cpxencoder_inval_address (l15_transducer_inval_address),
.l15_cpxencoder_cross_invalidate (l15_transducer_cross_invalidate),
.l15_cpxencoder_cross_invalidate_way (l15_transducer_cross_invalidate_way),
.l15_cpxencoder_inval_dcache_inval (l15_transducer_inval_dcache_inval),
Expand Down Expand Up @@ -834,6 +844,7 @@ l15_pipeline pipeline(
.mshr_pipe_readres_control_s1(mshr_pipe_readres_control_s1),
.mshr_pipe_readres_homeid_s1(mshr_pipe_readres_homeid_s1),
.mshr_pipe_vals_s1(mshr_pipe_vals_s1),
.mshr_pipe_ifill_address(mshr_pipe_ifill_address),
.mshr_pipe_ld_address(mshr_pipe_ld_address),
.mshr_pipe_st_address(mshr_pipe_st_address),
.mshr_pipe_st_way_s1(mshr_pipe_st_way_s1),
Expand Down
8 changes: 6 additions & 2 deletions piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv
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Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,7 @@ module l15_mshr(

// s1/2/3 (address conflict checking)
output reg [(`L15_NUM_MSHRID_PER_THREAD*`L15_NUM_THREADS)-1:0] mshr_pipe_vals_s1,
output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ifill_address,
output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_ld_address,
output reg [(40*`L15_NUM_THREADS)-1:0] mshr_pipe_st_address,
output reg [(2*`L15_NUM_THREADS)-1:0] mshr_pipe_st_way_s1,
Expand Down Expand Up @@ -118,7 +119,7 @@ reg [`L15_CONTROL_WIDTH-1:0] ld_control [0:`L15_NUM_THREADS-1];
reg [`L15_NUM_THREADS-1:0] ld_val;
reg [`PACKET_HOME_ID_WIDTH-1:0] ld_homeid [0:`L15_NUM_THREADS-1];

// reg [`L15_PADDR_HI:0] ifill_address [0:`L15_NUM_THREADS-1];
reg [`L15_PADDR_HI:0] ifill_address [0:`L15_NUM_THREADS-1];
reg [`L15_CONTROL_WIDTH-1:0] ifill_control [0:`L15_NUM_THREADS-1];
reg [`L15_NUM_THREADS-1:0] ifill_val;
// reg [`PACKET_HOME_ID_WIDTH-1:0] ifill_homeid [0:`L15_NUM_THREADS-1];
Expand Down Expand Up @@ -156,6 +157,7 @@ end
reg [`L15_NUM_MSHRID_PER_THREAD-1:0] tmp_vals [`L15_NUM_THREADS-1:0];
reg [`L15_PADDR_HI:0] tmp_st_address [`L15_NUM_THREADS-1:0];
reg [`L15_PADDR_HI:0] tmp_ld_address [`L15_NUM_THREADS-1:0];
reg [`L15_PADDR_HI:0] tmp_ifill_address [`L15_NUM_THREADS-1:0];
reg [2-1:0] tmp_st_way [`L15_NUM_THREADS-1:0];
reg [`L15_MESI_TRANS_STATE_WIDTH-1:0] tmp_st_state [`L15_NUM_THREADS-1:0];
always @ *
Expand All @@ -169,6 +171,7 @@ begin

tmp_st_address[THREADID] = st_address[THREADID];
tmp_ld_address[THREADID] = ld_address[THREADID];
tmp_ifill_address[THREADID] = ifill_address[THREADID];
tmp_st_way[THREADID] = st_way[THREADID];
tmp_st_state[THREADID] =st_state[THREADID];
'''
Expand All @@ -178,6 +181,7 @@ begin
print(tt)
%>
mshr_pipe_vals_s1 = {tmp_vals[1], tmp_vals[0]};
mshr_pipe_ifill_address = {tmp_ifill_address[1], tmp_ifill_address[0]};
mshr_pipe_ld_address = {tmp_ld_address[1], tmp_ld_address[0]};
mshr_pipe_st_address = {tmp_st_address[1], tmp_st_address[0]};
mshr_pipe_st_way_s1 = {tmp_st_way[1], tmp_st_way[0]};
Expand Down Expand Up @@ -238,7 +242,7 @@ begin
case (mshrid_s1)
`L15_MSHR_ID_IFILL:
begin
// ifill_address[threadid_s1] <= pipe_mshr_writereq_address_s1;
ifill_address[threadid_s1] <= pipe_mshr_writereq_address_s1;
ifill_control[threadid_s1] <= pipe_mshr_writereq_control_s1;
end
`L15_MSHR_ID_LD:
Expand Down
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