Aspiring Design Verification (DV) Engineer | VLSI Enthusiast
B.Tech @ Siddhartha Institute of Engineering and Technology
DV Training @ VLSIGURU, Bengaluru (Sept 2025 – Present)
📧 praveentech56@gmail.com | 🐙 GitHub
I am a fresher VLSI Design Verification engineer currently undergoing hands-on DV training at VLSIGURU, Bengaluru. My focus is on writing robust, reusable verification environments using SystemVerilog and UVM to verify RTL designs. I am actively looking for DV internship and full-time opportunities.
- UVM Testbench Architecture (Agent, Driver, Monitor, Scoreboard, Coverage)
- Functional & Code Coverage
- SystemVerilog Assertions (SVA)
- Constrained Random Verification (CRV)
- Protocol Verification — AXI4 / AXI4-Lite
| Project | Description | Tech |
|---|---|---|
| Memory Controller Verification | UVM-based verification of a memory controller with full read/write/reset coverage | SV, UVM |
| Asynchronous FIFO Verification | Verified async FIFO across clock domain crossing scenarios with SVA & coverage | SV, UVM |
| Interrupt Controller Verification | Functional verification of an interrupt controller with priority & masking tests | SV, UVM |
| AXI4-Lite Protocol Verification | Feature validation of AXI4-Lite — read/write channels, handshaking, error responses | SV, UVM |
- B.Tech — Siddhartha Institute of Engineering and Technology, Ibrahimpatnam
- CGPA - 7.05/10
- DV Training — VLSIGURU, Bengaluru (Sept 2025 – Present)
- Hands-on UVM testbench development
- Protocol verification (AXI)
- RTL design & verification flows
I'm actively looking for DV internships and entry-level opportunities in VLSI/semiconductor companies.
"Verification is not just about finding bugs — it's about building confidence in silicon."