Fix copper layer ordering and add geometry filters, pad-distance limiting, and stackup snapshots

[PoeAlex]

Motivation

• Correct incorrect Top/Bottom layer indexing so physics and plots use the true stackup order instead of relying on sorted layer IDs.
• Reduce runtime and memory by optionally restricting the simulation grid to a radius around selected pads via a pad-distance limit.
• Allow users to filter geometry so mapping focuses on relevant nets by ignoring long traces or polygons not attached to the selected pads.
• Produce richer snapshot/preview output by exporting a full stackup visualization including heatsink contours instead of single top/bottom images.

Description

• Replace naive copper-layer scanning with stackup-aware ordering using board.GetCopperLayerCount() and building ordered_ids from pcbnew.F_Cu, pcbnew.In?_Cu, and pcbnew.B_Cu so top/bottom indices are correct.
• Add geometry filter UI and settings: Ignore Traces, Ignore Polygons Not Attached to Selected Pads, Limit Area to Pads, and Limit Distance (mm), and wire them into SettingsDialog and preview generation.
• Limit the simulation bounds when pad-area limiting is enabled, and pass pads_list into create_multilayer_maps and generate_preview; implement build_pad_distance_mask and apply area_mask so K, V, H and polygon HitTestFilledArea respect the pad-distance limit.
• Preserve vias when ignoring traces, selectively filter zones by pad net name/code, change save_snapshot to _save_stackup_plot (multi-layer export with heatsink contours), and apply minor stability/perf tweaks like reusing v_chg and precomputing z_eff.

Testing

• No automated tests were run because the plugin requires the KiCad runtime and actual board data to exercise mapping and preview features.

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Codex Task