A robust, efficient, low-latency speech-to-text library with advanced voice activity detection, wake word activation and instant transcription.

iCESugar series FPGA dev board

A minimum configuration for Neovim targeting SystemVerilog that provides configuration for plugin management, a language server, tree-sitter, and linting

Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats

SystemVerilog synthesis tool

A simple RISC V core for teaching

Online demonstration for DigitalJS

Improve keyboard comfort and usability with advanced customization

sensible.vim: Defaults everyone can agree on

Bitbanged DVI on the RP2040 Microcontroller

Cross-platform Rust rewrite of the GNU coreutils

fugitive.vim: A Git wrapper so awesome, it should be illegal

Verilog library for ASIC and FPGA designers

🔍 A Hex Editor for Reverse Engineers, Programmers and people who value their retinas when working at 3 AM.

Port Allwinner xradio driver to mainline Linux.

NixOS port for OrangePi R1 Plus. WIP

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Functional verification project for the CORE-V family of RISC-V cores.

Scope Graph Implementation in Rust

Toolchain for the 8-bit TTL-CPU - http://digitarworld.uw.hu/ttlcpu.html