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Update the clock gating primitive for Verilator v5.0 #144

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merged 1 commit into from
Sep 19, 2023
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Update the clock gating primitive for Verilator v5.0 #144

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9 changes: 8 additions & 1 deletion src/main/resources/STD_CLKGT_func.v
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Original file line number Diff line number Diff line change
Expand Up @@ -10,11 +10,18 @@ module STD_CLKGT_func (

assign clk_en = E | TE;

`ifdef VERILATOR_5
always @(CK or clk_en) begin
if (CK == 1'b0)
clk_en_reg <= clk_en;
end
`else
always @(posedge CK)
begin
clk_en_reg = clk_en;
end
`endif

assign Q = CK & clk_en_reg;

endmodule // Copy from Xihu
endmodule