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top-down: do not use boring utils #143

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Sep 14, 2023
Merged

top-down: do not use boring utils #143

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923431e
top-down: do not use boring utils
Tang-Haojin Sep 14, 2023
c51801d
top-down: remove DontCare in io initialization
Tang-Haojin Sep 14, 2023
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15 changes: 10 additions & 5 deletions src/main/scala/huancun/HuanCun.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -244,6 +244,10 @@ class HuanCun(implicit p: Parameters) extends LazyModule with HasHuanCunParamete
val io = IO(new Bundle {
val perfEvents = Vec(banks, Vec(numPCntHc,Output(UInt(6.W))))
val ecc_error = Valid(UInt(64.W))
val debugTopDown = new Bundle {
val robHeadPaddr = Vec(cacheParams.hartIds.length, Flipped(Valid(UInt(36.W))))
val addrMatch = Vec(cacheParams.hartIds.length, Output(Bool()))
}
})

val sizeBytes = cacheParams.toCacheParams.capacity.toDouble
Expand Down Expand Up @@ -415,15 +419,16 @@ class HuanCun(implicit p: Parameters) extends LazyModule with HasHuanCunParamete
case EdgeOutKey => node.out.head._2
case BankBitsKey => bankBits
})))
topDownOpt.foreach {
_ => {
topDown.get.io.msStatus.zip(slices).foreach {
topDown match {
case Some(t) =>
t.io.msStatus.zip(slices).foreach {
case (in, s) => in := s.io.ms_status.get
}
topDown.get.io.dirResult.zip(slices).foreach {
t.io.dirResult.zip(slices).foreach {
case (res, s) => res := s.io.dir_result.get
}
}
t.io.debugTopDown <> io.debugTopDown
case None => io.debugTopDown.addrMatch.foreach(_ := false.B)
}
}

Expand Down
17 changes: 7 additions & 10 deletions src/main/scala/huancun/TopDownMonitor.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -12,17 +12,16 @@ class TopDownMonitor()(implicit p: Parameters) extends HuanCunModule {
val io = IO(new Bundle() {
val dirResult = Vec(banks, Flipped(ValidIO(new DirResult)))
val msStatus = Vec(banks, Vec(mshrsAll, Flipped(ValidIO(new MSHRStatus))))
val debugTopDown = new Bundle {
val robHeadPaddr = Vec(cacheParams.hartIds.length, Flipped(Valid(UInt(36.W))))
val addrMatch = Vec(cacheParams.hartIds.length, Output(Bool()))
}
})

/* ====== PART ONE ======
* Check whether the Addr given by core is a Miss in Cache
*/
for (hartId <- cacheParams.hartIds) {
val perfName = s"${cacheParams.name}MissMatch_${hartId}"

val pAddr = WireInit(0.U.asTypeOf(Valid(UInt(36.W)))) // TODO: hand written to match PAddrBits in SoC.scala
ExcitingUtils.addSink(pAddr, s"rob_head_paddr_${hartId}", ExcitingUtils.Perf)

for (((hartId, pAddr), addrMatch) <- cacheParams.hartIds zip io.debugTopDown.robHeadPaddr zip io.debugTopDown.addrMatch) {
val addrMatchVec = io.msStatus.zipWithIndex.map {
case(slice, i) =>
slice.map {
Expand All @@ -36,10 +35,8 @@ class TopDownMonitor()(implicit p: Parameters) extends HuanCunModule {
}
}

val addrMatch = Cat(addrMatchVec.flatten).orR

XSPerfAccumulate(cacheParams, perfName, addrMatch)
ExcitingUtils.addSource(addrMatch, perfName, ExcitingUtils.Perf)
addrMatch := Cat(addrMatchVec.flatten).orR
XSPerfAccumulate(cacheParams, s"${cacheParams.name}MissMatch_${hartId}", addrMatch)
}

/* ====== PART TWO ======
Expand Down