Merge pull request #34 from OpenXiangShan/late_release

Evict on refill

src/main/scala/coupledL2/Common.scala

@@ -51,9 +51,8 @@ class TaskBundle(implicit p: Parameters) extends L2Bundle with HasChannelBits {
   val size = UInt(msgSizeBits.W)
   val sourceId = UInt(sourceIdBits.W)     // tilelink sourceID
   val bufIdx = UInt(bufIdxBits.W)         // idx of SinkC buffer
-  val needProbeAckData = Bool()           // only used for SinkB reqs
+  val needProbeAckData = Bool()           // only used for SinkB reqs, whether L3 needs probeAckData
 
-  // val mshrOpType = UInt(mshrOpTypeBits.W) // type of the MSHR task operation
   // MSHR may send Release(Data) or Grant(Data) or ProbeAck(Data) through Main Pipe
   val mshrTask = Bool()                   // is task from mshr
   val mshrId = UInt(mshrBits.W)           // mshr entry index (used only in mshr-task)
@@ -78,9 +77,14 @@ class TaskBundle(implicit p: Parameters) extends L2Bundle with HasChannelBits {
   val tagWen = Bool()
   val dsWen = Bool()
 
-  // for Dir to choose a way not occupied by some unfinished MSHR task
+  // for Dir to choose a way inside wayMask
   val wayMask = UInt(cacheParams.ways.W)
 
+  // for Grant to read replacer to choose a replaced way
+  // for Release to read refillBuf and write to DS
+  val replTask = Bool()
+
+  // for TopDown Monitor (# TopDown)
   val reqSource = UInt(MemReqSource.reqSourceBits.W)
 
   def hasData = opcode(0)
@@ -89,39 +93,44 @@ class TaskBundle(implicit p: Parameters) extends L2Bundle with HasChannelBits {
 class PipeStatus(implicit p: Parameters) extends L2Bundle with HasChannelBits
 
 class PipeEntranceStatus(implicit p: Parameters) extends L2Bundle {
-  val tags = Vec(3, UInt(tagBits.W))
-  val sets = Vec(3, UInt(setBits.W))
+  val tags = Vec(4, UInt(tagBits.W))
+  val sets = Vec(4, UInt(setBits.W))
 
   def c_tag = tags(0)
   def b_tag = tags(1)
   def a_tag = tags(2)
+  def g_tag = tags(3) // replRead-Grant
 
   def c_set = sets(0)
   def b_set = sets(1)
   def a_set = sets(2)
+  def g_set = sets(3)
 }
 
 // MSHR exposes signals to MSHRCtl
 class MSHRStatus(implicit p: Parameters) extends L2Bundle with HasChannelBits {
-  val set = UInt(setBits.W)
-  val tag = UInt(tagBits.W)
-  val way = UInt(wayBits.W)
-  val off = UInt(offsetBits.W)
-  val opcode = UInt(3.W)
-  val param = UInt(3.W)
-  val size = UInt(msgSizeBits.W)
-  val source = UInt(sourceIdBits.W)
-  val alias = aliasBitsOpt.map(_ => UInt(aliasBitsOpt.get.W))
-  val aliasTask = aliasBitsOpt.map(_ => Bool())
-  val nestB = Bool()
-  val needProbeAckData = Bool() // only for B reqs
-  val pbIdx = UInt(mshrBits.W)
+  val set         = UInt(setBits.W)
+  val reqTag      = UInt(tagBits.W)
+  val metaTag     = UInt(tagBits.W)
+  val needsRepl = Bool()
   val w_c_resp = Bool()
   val w_d_resp = Bool()
   val w_e_resp = Bool()
-  val fromL2pft = prefetchOpt.map(_ => Bool())
-  val needHint = prefetchOpt.map(_ => Bool())
   val will_free = Bool()
+
+  //  val way = UInt(wayBits.W)
+//  val off = UInt(offsetBits.W)
+//  val opcode = UInt(3.W)
+//  val param = UInt(3.W)
+//  val size = UInt(msgSizeBits.W)
+//  val source = UInt(sourceIdBits.W)
+//  val alias = aliasBitsOpt.map(_ => UInt(aliasBitsOpt.get.W))
+//  val aliasTask = aliasBitsOpt.map(_ => Bool())
+//  val needProbeAckData = Bool() // only for B reqs
+//  val pbIdx = UInt(mshrBits.W)
+//  val fromL2pft = prefetchOpt.map(_ => Bool())
+//  val needHint = prefetchOpt.map(_ => Bool())
+
   // for TopDown usage
   val reqSource = UInt(MemReqSource.reqSourceBits.W)
   val is_miss = Bool()
@@ -135,16 +144,25 @@ class MSHRRequest(implicit p: Parameters) extends L2Bundle {
   val task = new TaskBundle()
 }
 
-// MSHR to ReqBuf for block info
-class MSHRBlockAInfo(implicit p: Parameters) extends L2Bundle {
+// MSHR info to ReqBuf and SinkB
+class MSHRInfo(implicit p: Parameters) extends L2Bundle {
   val set = UInt(setBits.W)
   val way = UInt(wayBits.W)
   val reqTag = UInt(tagBits.W)
   val willFree = Bool()
 
-  // to block Acquire for data about to be replaced until Release done
+  // to block Acquire for to-be-replaced data until Release done (indicated by ReleaseAck received)
   val needRelease = Bool()
+  // MSHR needs to send ReleaseTask but has not yet sent it
+  // PS: ReleaseTask is also responsible for writing refillData to DS when A miss
+  val releaseNotSent = Bool()
+
   val metaTag = UInt(tagBits.W)
+  val dirHit = Bool()
+
+  // decide whether can nest B (req same-addr) or merge B with release (meta same-addr)
+  val nestB = Bool()
+  val mergeB = Bool()
 
   // to drop duplicate prefetch reqs
   val isAcqOrPrefetch = Bool()
@@ -174,8 +192,8 @@ class FSMState(implicit p: Parameters) extends L2Bundle {
   val s_release = Bool()  // release downwards
   val s_probeack = Bool() // respond probeack downwards
   val s_refill = Bool()   // respond grant upwards
-  // val s_grantack = Bool() // respond grantack downwards
-  // val s_writeback = Bool()// writeback tag/dir
+  val s_merge_probeack = Bool() // respond probeack downwards, Probe merge into A-replacement-Release
+  // val s_grantack = Bool() // respond grantack downwards, moved to GrantBuf
   // val s_triggerprefetch = prefetchOpt.map(_ => Bool())
 
   // wait
@@ -189,8 +207,7 @@ class FSMState(implicit p: Parameters) extends L2Bundle {
   val w_grant = Bool()
   val w_releaseack = Bool()
   val w_grantack = Bool()
-
-  val w_release_sent = Bool()
+  val w_replResp = Bool()
 }
 
 class SourceAReq(implicit p: Parameters) extends L2Bundle {
@@ -215,17 +232,16 @@ class SourceBReq(implicit p: Parameters) extends L2Bundle {
 }
 
 class BlockInfo(implicit p: Parameters) extends L2Bundle {
+  val blockG_s1 = Bool()
   val blockA_s1 = Bool()
   val blockB_s1 = Bool()
   val blockC_s1 = Bool()
 }
 
+// used for nested C Release
 class NestedWriteback(implicit p: Parameters) extends L2Bundle {
   val set = UInt(setBits.W)
   val tag = UInt(tagBits.W)
-  val b_toN = Bool()
-  val b_toB = Bool()
-  val b_clr_dirty = Bool()
   val c_set_dirty = Bool()
 }
 

src/main/scala/coupledL2/CoupledL2.scala

@@ -49,12 +49,9 @@ trait HasCoupledL2Parameters {
                   else cacheParams.clientCaches.head.aliasBitsOpt
   val pageOffsetBits = log2Ceil(cacheParams.pageBytes)
 
-  val bufBlocks = 8 // hold data that flows in MainPipe
+  val bufBlocks = 4 // hold data that flows in MainPipe
   val bufIdxBits = log2Up(bufBlocks)
 
-  // 1 cycle for sram read, and latch for another cycle
-  val sramLatency = 2
-
   val releaseBufWPorts = 3 // sinkC and mainpipe s5, s6
 
   // Prefetch

src/main/scala/coupledL2/DataStorage.scala

@@ -59,5 +59,7 @@ class DataStorage(implicit p: Parameters) extends L2Module {
   array.io.w.apply(wen, io.wdata, arrayIdx, 1.U)
   array.io.r.apply(ren, arrayIdx)
 
-  io.rdata := RegNextN(array.io.r.resp.data(0), sramLatency - 1)
+  // TODO: timing: we should not use reg here, instead set this as multicycle path
+  // s3 read, s4 pass and s5 to destination
+  io.rdata := RegNextN(array.io.r.resp.data(0), 1)
 }