feat: add performance counters (#29)

* feat: add performance counters

* fix late_prefetch counter

* remove a_req_need_replacement counter

Now replacement is decided at MSHR Grant

* add caption to refillData === zero counter

---------

Co-authored-by: Chen Xi <48302201+Ivyfeather@users.noreply.github.com>

src/main/scala/coupledL2/MainPipe.scala

@@ -638,9 +638,6 @@ class MainPipe(implicit p: Parameters) extends L2Module {
     (req_s3.opcode === AcquireBlock || req_s3.opcode === AcquirePerm))
   XSPerfAccumulate(cacheParams, "get_miss", miss_s3 && req_s3.fromA && req_s3.opcode === Get)
 
-  XSPerfAccumulate(cacheParams, "a_req_need_replacement",
-    io.toMSHRCtl.mshr_alloc_s3.valid && !alloc_state.s_release)
-
   XSPerfAccumulate(cacheParams, "b_req_hit", hit_s3 && req_s3.fromB)
   XSPerfAccumulate(cacheParams, "b_req_miss", miss_s3 && req_s3.fromB)
 
@@ -681,6 +678,8 @@ class MainPipe(implicit p: Parameters) extends L2Module {
       XSPerfAccumulate(cacheParams, "get_trigger_prefetch_on_hit_pft", io.prefetchTrain.get.fire() && req_get_s3 && dirResult_s3.hit && meta_s3.prefetch.get)
   }
 
+  XSPerfAccumulate(cacheParams, "early_prefetch", meta_s3.prefetch.getOrElse(false.B) && !meta_s3.accessed && !dirResult_s3.hit && task_s3.valid)
+
   /* ===== Monitor ===== */
   io.toMonitor.task_s2 := task_s2
   io.toMonitor.task_s3 := task_s3

src/main/scala/coupledL2/RefillUnit.scala

@@ -22,6 +22,7 @@ import chisel3.util._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import chipsalliance.rocketchip.config.Parameters
+import coupledL2.utils.XSPerfAccumulate
 
 class grantAckQEntry(implicit p: Parameters) extends L2Bundle {
   val source = UInt(sourceIdBits.W)
@@ -70,4 +71,17 @@ class RefillUnit(implicit p: Parameters) extends L2Module {
   dontTouch(io.resp.respInfo.isHit)
 
   io.sinkD.ready := true.B
+
+  // count refillData all zero
+  // (assume beat0 and beat1 of the same block always come continuously, no intersection)
+  val zero = RegInit(true.B)
+  when (io.refillBufWrite.valid) {
+    when (beat === beatSize.U) {
+      zero := true.B // init as true
+    } .otherwise {
+      zero := zero & io.sinkD.bits.data === 0.U // if beat not 0.U, clear 'zero'
+    }
+  }
+  XSPerfAccumulate(cacheParams, "sinkD_from_L3_zero", io.refillBufWrite.valid && beat === beatSize.U && zero && io.sinkD.bits.data === 0.U)
+  XSPerfAccumulate(cacheParams, "sinkD_from_L3_all",  io.refillBufWrite.valid && beat === beatSize.U)
 }

src/main/scala/coupledL2/RequestBuffer.scala

@@ -223,7 +223,7 @@ class RequestBuffer(flow: Boolean = true, entries: Int = 4)(implicit p: Paramete
 
   // add XSPerf to see how many cycles the req is held in Buffer
   if(cacheParams.enablePerf) {
-    XSPerfAccumulate(cacheParams, "drop_prefetch", dup)
+    XSPerfAccumulate(cacheParams, "drop_prefetch", dup) // this also serves as late prefetch
     if(flow){
       XSPerfAccumulate(cacheParams, "req_buffer_flow", doFlow)
     }

src/main/scala/coupledL2/SinkA.scala

@@ -159,7 +159,12 @@ class SinkA(implicit p: Parameters) extends L2Module {
     (io.task.bits.opcode === PutFullData || io.task.bits.opcode === PutPartialData))
   XSPerfAccumulate(cacheParams, "sinkA_put_beat", io.a.fire() &&
     (io.a.bits.opcode === PutFullData || io.a.bits.opcode === PutPartialData))
-  prefetchOpt.foreach { _ => XSPerfAccumulate(cacheParams, "sinkA_prefetch_req", io.prefetchReq.get.fire()) }
+  prefetchOpt.foreach {
+    _ =>
+      XSPerfAccumulate(cacheParams, "sinkA_prefetch_req", io.prefetchReq.get.fire)
+      XSPerfAccumulate(cacheParams, "sinkA_prefetch_from_l2", io.prefetchReq.get.bits.isBOP && io.prefetchReq.get.fire)
+      XSPerfAccumulate(cacheParams, "sinkA_prefetch_from_l1", !io.prefetchReq.get.bits.isBOP && io.prefetchReq.get.fire)
+  }
 
   // cycels stalled by mainpipe
   val stall = io.task.valid && !io.task.ready