utility: use unified MemReqSource (#44)

src/main/scala/coupledL2/Common.scala

@@ -20,8 +20,8 @@ package coupledL2
 import chisel3._
 import chisel3.util._
 import chipsalliance.rocketchip.config.Parameters
-
 import freechips.rocketchip.tilelink.TLPermissions._
+import utility.MemReqSource
 
 abstract class L2Module(implicit val p: Parameters) extends MultiIOModule with HasCoupledL2Parameters
 abstract class L2Bundle(implicit val p: Parameters) extends Bundle with HasCoupledL2Parameters
@@ -252,21 +252,3 @@ class PrefetchRecv extends Bundle {
 class L2ToL1Hint(implicit p: Parameters) extends Bundle {
   val sourceId = UInt(32.W)    // tilelink sourceID
 }
-
-// indicates where the memory access request comes from
-// a dupliacte of this is in xiangShan/package.scala utility/TLUtils/BusKeyField.scala
-object MemReqSource extends Enumeration {
-  val NoWhere = Value("NoWhere")
-
-  val CPUInst = Value("CPUInst")
-  val CPULoadData = Value("CPULoadData")
-  val CPUStoreData = Value("CPUStoreData")
-  val CPUAtomicData = Value("CPUAtomicData")
-  val L1InstPrefetch = Value("L1InstPrefetch")
-  val L1DataPrefetch = Value("L1DataPrefetch")
-  val PTW = Value("PTW")
-  val L2Prefetch = Value("L2Prefetch")
-  val ReqSourceCount = Value("ReqSourceCount")
-
-  val reqSourceBits = log2Ceil(ReqSourceCount.id)
-}

src/main/scala/coupledL2/L2Param.scala

@@ -25,8 +25,7 @@ import freechips.rocketchip.util._
 import chipsalliance.rocketchip.config.Field
 import huancun.CacheParameters
 import coupledL2.prefetch._
-import MemReqSource._
-import utility.ReqSourceKey
+import utility.{MemReqSource, ReqSourceKey}
 
 // General parameter key of CoupledL2
 case object L2ParamKey extends Field[L2Param](L2Param())

src/main/scala/coupledL2/MSHR.scala

@@ -20,7 +20,7 @@ package coupledL2
 import chisel3._
 import chisel3.util._
 import coupledL2.MetaData._
-import utility.{ParallelLookUp, ParallelPriorityMux}
+import utility.{MemReqSource, ParallelLookUp, ParallelPriorityMux}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import freechips.rocketchip.tilelink.TLPermissions._

src/main/scala/coupledL2/SinkA.scala

@@ -25,6 +25,7 @@ import freechips.rocketchip.tilelink.TLMessages._
 import freechips.rocketchip.tilelink.TLHints._
 import coupledL2.prefetch.PrefetchReq
 import coupledL2.utils.XSPerfAccumulate
+import utility.MemReqSource
 
 class SinkA(implicit p: Parameters) extends L2Module {
   val io = IO(new Bundle() {

src/main/scala/coupledL2/SinkB.scala

@@ -23,6 +23,7 @@ import chipsalliance.rocketchip.config.Parameters
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import coupledL2.utils.XSPerfAccumulate
+import utility.MemReqSource
 
 class BMergeTask(implicit p: Parameters) extends L2Bundle {
   val id = UInt(mshrBits.W)

src/main/scala/coupledL2/SinkC.scala

@@ -23,6 +23,7 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import chipsalliance.rocketchip.config.Parameters
 import coupledL2.utils.XSPerfAccumulate
+import utility.MemReqSource
 
 class PipeBufferRead(implicit p: Parameters) extends L2Bundle {
   val bufIdx = UInt(bufIdxBits.W)

src/main/scala/coupledL2/TopDownMonitor.scala

@@ -20,6 +20,7 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import coupledL2.utils.{XSPerfAccumulate, XSPerfHistogram, XSPerfRolling}
+import utility.MemReqSource
 
 class TopDownMonitor()(implicit p: Parameters) extends L2Module {
   val banks = 1 << bankBits