update

OpenTimer · Jan 4, 2019 · 0e0331e · 0e0331e
1 parent 04eb284
commit 0e0331e
Showing 1 changed file with 1 addition and 6 deletions.
diff --git a/README.md b/README.md
@@ -10,12 +10,7 @@ digital circuit. Below is a circuit written in Verilog.
 <img src="image/circuit.png" height="100%" width="40%" align="right"> 
 
 ```Verilog 
-module simple (
-  input1,
-  input2, 
-  input3,
-  out
-);
+module simple (input1, input2, input3, out);
 
 // primary inputs
 input input1;