UART Lite Peripheral
Base Address
0x0400_4000
Description
Simple polling-based UART peripheral supporting basic transmit and receive operations.
Registers
| Offset |
Register |
R/W |
Description |
| 0x00 |
TXDATA |
W |
Transmit byte |
| 0x04 |
RXDATA |
R |
Received byte |
| 0x08 |
STATUS |
R |
UART status |
| 0x0C |
BAUDDIV |
R/W |
Baud rate divider |
Expected Ports
input uart_rx
output uart_tx
Requirements
Support 8-bit data transfers.
Configurable baud rate through BAUDDIV register.
Software writes TXDATA to initiate transmission.
Received data shall be readable through RXDATA.
STATUS register shall indicate transmitter readiness and receive availability.
Peripheral must be memory-mapped through the PicoSoC external MMIO interface.
Include firmware validation example.
Include simulation support using the standard PicoSoC verification flow.
UART Lite Peripheral
Base Address
0x0400_4000Description
Simple polling-based UART peripheral supporting basic transmit and receive operations.
Registers
Expected Ports
Requirements
Support 8-bit data transfers.
Configurable baud rate through BAUDDIV register.
Software writes TXDATA to initiate transmission.
Received data shall be readable through RXDATA.
STATUS register shall indicate transmitter readiness and receive availability.
Peripheral must be memory-mapped through the PicoSoC external MMIO interface.
Include firmware validation example.
Include simulation support using the standard PicoSoC verification flow.