Instructions: Separate rocket custom instructions

As standard instructions are synced from riscv-opcodes
OpenRigil · Apr 2, 2022 · cfac7a5 · cfac7a5
1 parent 21f1ec1
commit cfac7a5
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diff --git a/src/main/scala/rocket/CustomInstructions.scala b/src/main/scala/rocket/CustomInstructions.scala
@@ -0,0 +1,12 @@
+// See LICENSE.SiFive for license details.
+// See LICENSE.Berkeley for license details.
+
+package freechips.rocketchip.rocket
+
+import Chisel._
+
+object CustomInstructions {
+  def CEASE              = BitPat("b00110000010100000000000001110011")
+  def CFLUSH_D_L1        = BitPat("b111111000000?????000000001110011")
+  def CDISCARD_D_L1      = BitPat("b111111000010?????000000001110011")
+}
diff --git a/src/main/scala/rocket/IDecode.scala b/src/main/scala/rocket/IDecode.scala
@@ -9,6 +9,7 @@ import freechips.rocketchip.tile.HasCoreParameters
 import freechips.rocketchip.util._
 import freechips.rocketchip.scie.SCIE
 import Instructions._
+import CustomInstructions._
 import ALU._
 
 abstract trait DecodeConstants extends HasCoreParameters