Skip to content

update riscv intrinsics for latest spec #3919

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Mar 15, 2023
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
15 changes: 9 additions & 6 deletions common_riscv64.h
Original file line number Diff line number Diff line change
Expand Up @@ -91,12 +91,15 @@ static inline int blas_quickdivide(blasint x, blasint y){
#define BUFFER_SIZE ( 32 << 20)
#define SEEK_ADDRESS

#if defined(C910V)
#include <riscv_vector.h>
#endif

#if defined(x280)
#include <riscv_vector.h>
#if defined(C910V) || defined(RISCV64_ZVL256B) || defined(__riscv_v)
# include <riscv_vector.h>
# if !defined(DOUBLE)
# define EXTRACT_FLOAT(v) __riscv_vfmv_f_s_f32m1_f32(v)
# else
# define EXTRACT_FLOAT(v) __riscv_vfmv_f_s_f64m1_f64(v)
# endif
#else
# define EXTRACT_FLOAT(v) (v[0])
#endif

#endif
10 changes: 5 additions & 5 deletions cpuid_riscv64.c
Original file line number Diff line number Diff line change
Expand Up @@ -70,14 +70,14 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
/* or implied, of The University of Texas at Austin. */
/*********************************************************************/

#define CPU_GENERIC 0
#define CPU_C910V 1
#define CPU_x280 2
#define CPU_GENERIC 0
#define CPU_C910V 1
#define CPU_RISCV64_ZVL256B 2

static char *cpuname[] = {
"RISCV64_GENERIC",
"C910V"
"x280"
"C910V",
"CPU_RISCV64_ZVL256B"
};

int detect(void){
Expand Down
Loading