Add A&B hardware description

[amoutenet]

Add Alice & Bob hardware description in main README.md file.

[amoutenet]

@lprost Hey Laurent, could you please have a look at what I wrote regarding A&B architecture and the links I put to see if it looks good to you? Thanks!

[lprost]

Hi Alice, looks very nice to me, it's a good idea to link the whitepaper! Shall we give a short intro concerning how the tools are meant to be used? The general idea would be:

• First make sure your circuit runs with the built-in Pennylane emulator
• Then, try to compile it to the gate set of logical qubits by targeting the LOGICAL_NOISELESS backend, study how this affects circuit size and what you can do to optimize that
• Then, study how noise impacts the quality of the results by creating custom logical backends (see the swap test notebook for inspiration)
• Then, for problem instances that are too big to be emulated (warning: noisy emulation is slower than noiseless), try some resource estimation to assess the size of the hardware that will be required to run your case

[amoutenet]

@lprost Indeed I thought about adding these steps in the "technical objectives" below!

I think @jmichel80's initial idea was to start from Pennylane emulators and then move to "real hardware", but since here we will work with our emulators, we can insist to quickly move from Pennylane to A&B emulators. Wdyt?

[lprost]

Cool, will you do it then, or do you want me to do it?

As for moving quickly to our emulators, I think we just need to be careful about performance. Because compilation to the gate set of logical qubits will make circuits bigger, emulation will be slower, which might not be ideal for quick iterations. But depending on the size of the circuits they try, it might or might not be a problem. I guess you can adjust this live during the event.

Also, shall we say a word about experimenting with FTQC algorithms?